IP Network Measurement Division
7
40G Quick Start Guide
（
Jitter
）
D-FF
(4ch) PPG
D-FF
4:1 MUX
MP1803A 4:1 MUX
1/4
Divider
Delay
Delay
SG
40 GHz Clock Out
(Full rate clock)
40 Gbit/s Data Out
10 Gbit/s Data
40 GHz Clock In
40GHz full rate clock, DFF is used.
Æ
Bit length does not depend on clock’s duty cycle like systems using
half rate clock system.
Æ
Jitter modulation function is available with MP1797A Jitter Analyzer.
Full rate clock and 1/4 rate clock output is available within 140ps delay.
1/4 rate clock is delivered to 10G data generation.
Full rate clock can be delivered to Error Detector.
Input stage has 10Gbit/s DFF.
Æ
Delicate channel skew
adjustment is not needed.
10 GHz Clock
(1/4 rate clock)
Block Diagram of Multiplexer
Block Diagram of Multiplexer
IP Network Measurement Division
8
40G Quick Start Guide
（
Jitter
）
D-FF
D-FF
1:4 DEMUX
MP1804A 1:4 DEMUX
1/4
Divider
Delay
Threshold
10 Gbit/s Data Out
40 Gbit/s Data
40 GHz Clock
10 GHz Clock Out
Delay
AMP
Data threshold voltage and clock phase
adjustment function is available.
Æ
DC data can be detected.
Æ
Eye margin measurement is available.
Full rate clock is used at D-FF of the first stage.
Æ
Phase margin does not depend of input clock’s duty cycle.
Four of 1/4 rate clocks are output.
Æ
With MP1800A, All of 10G data
’
s error can
be detected simultaneously.
DEMUX Reset
Block Diagram of
Block Diagram of
Demultiplexer
Demultiplexer
4