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A1101R09x – User’s Manual
Release Date 05/08/12
1.3.
Features
Features:
Frequency range: 902-928 MHz
Ultra small package size
A1101R09C : 9mm x 12mm x 2.5mm
A1101R09A : 9mm x 16mm x 2.5mm
Impedance controlled multi-layer PCB
Shielded Package
1.8 to 3.6 V operation
SPI Interface
RoHS Compliant
LGA Footprint
Low Power Consumption
Regulatory approvals for FCC
Digital RSSI output
Programmable channel filter bandwidth
Programmable output power up to +10
dBm
High sensitivity (–104 dBm at 1.2
kBaud, 1% packet error rate)
Low current consumption (14.4 mA in
RX, 1.2kBaud, input well above
sensitivity limit)
Fast startup time: 240us from SLEEP
to Rx or Tx mode
Separate 64 byte Rx and Tx FIFOs
Data Rate: 1.2 – 500 Kbit/Sec
Programmable data rate from 1.2 to
500 kBaud
Sleep state: 0.2µA
Idle State: 1.7mA
Benefits Summary:
Operating temperature -40 to +85C
100% RF Tested in production
Common footprint for all family
members
No RF engineering experience
necessary
Only requires a 2 layer PCB
implementation
Excellent receiver selectivity and
blocking Performance
Suited for systems compliant with FCC
CFR47 Part 15.247a2 and 15.249 (US)
and Canada under Industry Canada
(IC) Radio Standards Specification
(RSS) RSS-210 and RSS-Gen.
No regulatory “Intentional radiator”
testing required to integrate module
into end product. Simple certification
labeling replaces testing.
1.4.
Theory of Operation
The A1101R09A and A1101R09C are for low power wireless applications in the US 902 –
928MHz ISM band. The devices can be used to implement a variety of networks, including;
point to point, point to multipoint, peer to peer and mesh networks.
The A1101R09A and A1101R09C both interface to an application microcontroller via an SPI
bus. Physical and MAC layer functionality are accessed via the SPI bus through addressable
registers as well as execution commands. Data received, or to be transmitted, are also
accessed through the SPI bus and are implemented as a FIFO register (64 bytes each for Tx
and Rx).
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