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Analogic DBS 8700, Hardware User Manual

The Analogic DBS 8700 Hardware User Manual is a essential guide for maximizing the potential of your device. Easily download the manual for free from our website to learn how to properly operate and maintain your DBS 8700. Get started with your device by accessing the manual at manualshive.com.

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Summary of Contents for DBS 8700

Page 1: ...s underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos...

Page 2: ...User sManual I I e n bus DBS 8700 8701 VMEIVXI DataAcquisition System The world esoun forP cisbn Signal Technology Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisa...

Page 3: ...4 START MODE 4 3 5 5 RUN AD DIAGS 4 3 5 6 GET DIAG ERROR 4 3 5 7 THRESHOLD 4 3 5 8 TRIGGER POLARITY 4 3 5 9 READ SRAM 4 3 5 10 TIMEOUT 4 3 5 11 GET ERROR 4 3 5 12 PRE POST TRIGGER 4 3 5 13 THRESHOLD...

Page 4: ...he productis returnedfor repair a copy of the original bill of sale or invoiceis sent with the product d Analogic will not be liablefor any incidentalor consequential damages e Inthe opinion of Analog...

Page 5: ...5 5 1 Registers 5 5 1 1 Chip LevelRegisters 5 5 1 2 Channel Level Registers 5 5 2 Commands 5 5 3 Chaining 5 5 4 Register Description 5 5 4 1 Master Mode Register 5 5 4 2 Command Register 5 5 4 3 Chain...

Page 6: ...DAS Data Output Format 2 2 5 VME Interrupt 2 2 6 TTLTRG Jumpers 2 2 7 Remote Triggering 2 2 8 Analog Signal Guard 2 3 EXTERNALSIGNAL INPUT 2 3 1 Analog Signals 2 3 2 Digital Signals 2 4 VMEBUS BACKPLA...

Page 7: ...e Stage Delay Example 5 13 5 10 Two Stage Delay Example 5 15 5 11 Three Stage Delay Example 5 15 5 12 Single Stage Delay Examplewith S H 5 17 5 13 Memory DeviceAttribute Register Format 5 18 5 14 Samp...

Page 8: ...er Base address 0006H 5 2 4 1 Loadingthe Scan Sequence RAM 5 2 4 2 GainIChannelWord 5 2 4 3 ChannelIPortWord 5 2 4 4 A Typical Sequence RAM LoadTable 5 2 4 5 SRAM Formatfor the DVX Family of Multiplex...

Page 9: ...lly reads the necessary information regarding data set size and memory buffer areas from the bus resident memory relieving the controlling micro processor of monitoring DMA operations Three flexible c...

Page 10: ...ppendix B NOTES ON DIELECTRICABSORPTION B 1 List of Tables Table Base Address Jumper Selection Examples Offset Binary Format Two s Complement Format Interrupt Level Selections TTLTRG Jumpers for Contr...

Page 11: ...umber is your authorization number Please write this number on your purchase order and shipping label Send all authorized returns to Analogic Corporation 8 Centennial Drive Peabody MA 01960 Attn Recei...

Page 12: ...is a detailed functional description of the cards and contains the necessary depth of information should a user choose to write his own driver Section 6 Specifications contains a detailed list of per...

Page 13: ...Level EXT TRIG to TTLTRG Line Control Signals to J36 Clock Configuratior J2 53 Remote Triggering J37 Not Used TTLTRG Unes signal Guard J4 J7 J9 J12 BaseAddress Format m Srqq Factory Use Only 3 2 1 JX...

Page 14: ...n exchange contact MCD Order Entry Tel 508 977 3000 Ext 3840 or 3844 FAX 508 977 6818 For technical assistance contact MCD Applications Engineers Tel 508 977 3000 Domestic calls Ext 3876 International...

Page 15: ...r Offset Binary install 58 2 to J8 3 To use Two s Complement install J8 1 to 58 2 Table 2 2 Offset Blnary Format 2 2 5 VME Interrupt Since the DAS requires a minimum of attention from the VME host pro...

Page 16: ...ecision Clock J36 installedfrom 2 3 ExternalTrigger Input J3 installedfrom 2 3 Two s Complement Data J8 installedfrom 1 2 InterruptLevel 1 J32 installed Analog Ground Signal Guards J200 installed2 3 E...

Page 17: ...while the slave card s should be configured to receive it The REMTRG signal must then be jumpered to one of the lTLTRG lines on the P2 connector see Table 2 5 Jumpers selections on the Master and Sla...

Page 18: ...nal precision clock from the Front Panel EXT TRIG input install 536 1 to J36 2 J9 J10 J12 J l l J7 56 J5 54 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT IN IN...

Page 19: ...rt and the E Trigger when both are provided by the user Figure 2 2 EXTTRlG vs EXT START Timing Minimum P ocl Z i External Clock EXTTRIG connector I ExternalTrigger EXT START connector Run 2 4 VMEBUSBA...

Page 20: ...AS card Fallure to comply with the Wlbus electrical speclflcatlons may result In damage to or unreliable operationof the DAS and companion cards If a companion card is used with the DAS TTLTRG jumpers...

Page 21: ...y dvxread dvxwrite i n t d v x i o c t l else define dvxopen nodev define dvxclose nodev define dvxstrategy nodev define dvxread nodev define dvxwrite nodev define d v i o c t l nodev endif Insert the...

Page 22: ...put Connections I Connector Pin No port 1 IN IN Guard 2 3 2 Digital Signals The DAS accepts either an external clock input EXT TRIG or an external trigger input EXT START via the front panel BNC conne...

Page 23: ...he system has identified the DAS hardware The driver will turn the PASSFAIL light on the DAS to green if the startup diagnostics have passed If the driver does NOT detect the DAS card then the only me...

Page 24: ...as described in the following paragraphs Figure 3 1 shows a typical directory configuration and shows at which level in the structure each step in the following paragaphs takes place It also shows wh...

Page 25: ...d 3will remain valid until the device is released or explicitly changed by the application 4 2 DEFAULT DEVICE CONFIGURATION When the DAS is opened by the host application the DAS default configuration...

Page 26: ...e base address of the board in the appropriate VME address space the interrupt priority and the interrupt vector The line for dvxmO allocates system memory in VME A24D16 address space for the Scan Seq...

Page 27: ...of the sequence RAM 4 3 4 READ FID BUFFER COUNT The READ call starts the acquisition process with previously loaded setup values The fid field is the file id returned from a prior call to the open rou...

Page 28: ...LOSE WRITE READ Table 4 1 DAS UNlX Drivers I I I I I iardware Function 4llocate the deviceand establish communication Release the device Initialize the DAS ChannelIGain Sequence R A M Acquire data fro...

Page 29: ...used for diagnostics The flag parameter specifies which block of 64 bytes of sequence RAM is returned 0 31 The base address of the sequence RAM to be read is calculated as flag 64 An error is returne...

Page 30: ...RDWR flag defined in the system include files If the call to the open routine was successful the driver will return an integer greater than zero which will be used as the file id parameter in subseque...

Page 31: ...lid device model number 1 Cannot access sequence RAM m Invalid threshold value n Attempt to assign trigger to multiple channels 0 See dvx2502io h for the complete list of error codes 4 5 DATA ACQUISIT...

Page 32: ...is greater than the allowable 10 bit value an error is returned in the user structure 4 3 5 3 CLOCK SOURCE The IOCTL CLOCK SOURCE command setslclears the external clock select bit in the DAS CSR acco...

Page 33: ...AMPLING SEQUENCE STRUCTURE FOR THE WRITE TO SRAM for i 0 i NCHAN i 1 SeqRam i Channel i SeqRam i Gain l only one gain per acquisition SeqRam i Trigger O 1 OPEN THE DEVICE fid open dev avO 0 RDWR if fi...

Page 34: ...r allow the signal at the input connector to pass through the input multiplexer to the input buffer The data parameter specifies the input type the include file dvx2502io h defines values for valid in...

Page 35: ...threshold of 3 16 of full scale in the positive direction the DMAC will store all subsequent data points in the Post trigger buffer The Pre trigger data buffer will be half of the total number of sam...

Page 36: ...averr int rate int thres struct SeqRam SeqRam 8 short dvxdata MAX SAMPLES int tsamp samp float avgvolts 8 NUMBER OF CHANNELS TO SAMPLE printf n tEnter Number of Channels scanf d NCHAN if NCHAN 8 print...

Page 37: ...GISTER rate 1000 divide by 1000 printf nSetting up rate divisor if ioctl fid RATE DlVlSOR rate O 1 ioctl fid GET ERROR averr O printf DEV1CE ERROR 3d nW averr exit 0 1 SELECT TRIGGER POLARITY AS POSIT...

Page 38: ...intf DEV1CE ERROR 3d nn averr exit 0 1 SELECT INPUT SIGNAL TYPE if io tl fid SET SIGNAZ1 TYPE sigtype O 1 ioctl fid GET ERROR averr 0 printf DEV1CE ERROR 3d nW averr exit 0 1 GET SOME DATA if read fid...

Page 39: ...ata Chan ld 4 3f Chan ld 4 3fn CHANl volts i CHAN2 volts i 11 POSTTRIGGER DATA for i t s a m p l i ctsamp i 2 printf n PostTrigger Data Chan ld 4 3f Chan ld 4 3f1 CHANl volts i l CHAN2 volts i close f...

Page 40: ...n tEnter Number of Samples per Channel scanf d samp total number of samples we use 2 channels SETUP SAMPLING SEQUENCE STRUCTURE FOR THE WRITE TO SRAM TWO channels are used with triggering enabled on...

Page 41: ...DBS 870018701 HardwareUser s Manual Figure5 1 DAS FunctionalBlock Diagram I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 42: ...SIZE TO 1 2 TOTAL No OF SAMPLES i tsamp l printf nSetting PreTrigger buffer size if ioctl fid PRE TRIG BUF SZ i O 1 t ioctl fid GET ERROR averr O printf DEV1CE ERROR 3d nM averr exit 0 1 GET SOME DAT...

Page 43: ...xternally you can supply both the sampling trigger and the start command by connecting the signals to the BNCs and downloading the necessary selection commands into the Command register In the data de...

Page 44: ...lable on the front panel Ten LEDs indicate the 8 bit binary channel code 1of 256 the PassFail condition of the board and the BUSY condition while acquisition is in progress On the rear of the card the...

Page 45: ...alls Most likely you will never need to directly examine the contents of any register The DAS has 9 control and status registers that can be located on any 64 byte boundary above COO0 hexadecimal in t...

Page 46: ...a software controlled Programmable Gain Amplifier PGA with gains of 1 5 4 or 8 The gain can be changed under sequencer control every conversion cycle allowing the user to dynamically check for maximu...

Page 47: ...e 16 such blocks on the DAS card only the most significant 12bits of the Offset register are required For example if the Sequence Ram were to be mapped into the A24 space at location 401000H the Offse...

Page 48: ...a before concatenating it with the post trigger data and then locate the beginning of a scan sequence in the pre trigger data set 5 1 4 VMC vxI Interface To comply with both the VMEbus and VXlbus Spec...

Page 49: ...annel to be sampled and the control code bits The scan sequence is loaded into the sequence RAM starting at the first location VMEbus offset address 0 When the sequencer encounters the loop back code...

Page 50: ...d only The bit assignments for the Control Register Write are defined in Figure 5 3 The bit assignments for the Status register Read are defined in Figure 5 4 At power on all bits in the Control Regis...

Page 51: ...ltiplexer card connected to the DAS must be loaded with the code of the first channel on that multiplexer card to be scanned This is accomplished by the construction of a Pre scan table that is loaded...

Page 52: ...r is not connected to a port then the port is a single channel port The Channel number is split between the GaidChannel word and the Channel Port Word he most significant two bits of the channel code...

Page 53: ...when the scan sequence is repeated The same process is repeated for the other two ports 5 2 4 8 Example of two Stage Delay Now using the same set of channels and ports let us construct a table with 2...

Page 54: ...iption Pre scanTable Channel Port 1 0 Figure5 11 Three Stage Delay Example DESIREDSCAN ORDER THREE STAGE SRAM LOAD Channel Port Channel Port 2 3 0 6 O T It 7 1 3 2 4 0 8 1 4 2 5 0 9 1 5 2 w 2 0 b 6 1...

Page 55: ...nning of the scan by inserting at the beginning of the SRAM load table the replication of the first entry with the control code for the assertion of the Ext S H for as many sample periods as required...

Page 56: ...00000 01001000 1000 0000 0100 1000 These word pairs assertthe External 0100 000 and Hold signal for 5 sample periods 1000 0000 0100 1000 4 2 10000000 11100010 5 2 1000 0000 1110 1010 3 2 Endof 1000000...

Page 57: ...mpling Rate Select Register Base address 000AH The Sampling Rate Register Figure 5 14 controls the external trigger and external clock inputs and determines the internal sampling clock frequency The b...

Page 58: ...igger pulse 1 Front panel external start EXT TRG TTLTRG Selectionfor Trigger 00 TTLTRG4 01 lTLTRG5 10 lTLTRG6 11 lTLTRG7 Enable PrecisionClock Selection 0 TTLTRG External PrecisionClock 1 InternalPrec...

Page 59: ...ata dependent triggering is invoked the ITLTRG is enabled and the triggering event has occurred This applies to both Pretpost and Post Trigger acquisitions The threshold value is a Binary value wherea...

Page 60: ...ld BaseAddress 6 Upper Addr Tag Field Lower Address Field Current Operation Count Base O eration Count 5 2 10 AM9516 DMA Controller DMAC Data Reglster Base address 000EH Readlwrite operationsto the DM...

Page 61: ...ically reload reinitialize at the end of an acquisition cycle The DMAC can acquire data in three different ways 1 Normal data acquisition 2 Post trigger acquisition and 3 PreFost trigger acquisition I...

Page 62: ...Supervisory Program Access Addr Mod 3E b Supervisory Data Access Addr Mod 3D c Non privileged Program Access Addr Mod 3A d Non privileged Data Access Addr Mod 39 5 4 INTERRUPT OPERATIONS The DAS can g...

Page 63: ...ed in the DAS Therefore only the registers that are meaningful in the DMA operations of the DAS are discussed 5 5 1 Registers 5 5 1 1 Chip Level Registers Three global registers configure the chip fun...

Page 64: ...ption Table 5 2 lists the registers used their accessibility and their ad dresses The following is a detailed description of the bit assign ments and usage 5 5 4 1 Master Mode Register This 8 bit regi...

Page 65: ...n a channel begins a chaining operation the Chain Control Register Figure 5 17 is loaded with the Reload word from the memory location indicated by the address in the Chain Address register The bits i...

Page 66: ...ion and the action to be taken upon the completion or the abnormal termination of the operation Figure 5 18 Channel Mode Register Format Software e u e s t Hardware Mask 0 Reset 0 Accept hardware requ...

Page 67: ...aborted due to abnormal conditions the channel will generate an interrupt to the host processor A bit set in the B C RELOAD field causes the Base Address and Base Operations Count registers to be cop...

Page 68: ...d into the Current Address Registers A B 5 5 4 7 Current Operatlon Count Registers This 16 bit register contains the number of words to be transferred during a DMA operation With each transfer the con...

Page 69: ...VMEbus L No Auto Reload or Chain Set when DMA operation is complete and no Auto Chain Base to CurrentReload Rest or Ext Abort ChainAbort Set by Reset or Ext Abort chain address loaded 5 5 4 10 lnterr...

Page 70: ...ring chaining are located The contents are shown below Figure 5 22 Chain Address Register Format I 15 0 LowerAddress 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 4 12 Chain Control Register The first step in a cha...

Page 71: ...define WordCount OxOfff int DataTablAdrL DataTablAdrH long DataTableAddr ChainAddrl ChainAddr2 int WordCount IntrVect int ChanModeH ChanModeL RESET THE 9516A CONTROLLER set the software reset bit Writ...

Page 72: ...Mem ChainAddr2 1 DataTablAdrH WriteMem ChainAddr2 2 DataTablAdrL write word count write channel mode words ChanModeH 0x0004 interrupt on Terminal Count after reading the chaining table ChanModeL 0x025...

Page 73: ...rH WriteMem ChainAddr1 5 DataTablAdrL write base word count WriteMem ChainAddr1 6 WordCount write channel mode words ChanModeH 0x0004 interrupt on terminal count after reading the chaining table ChanM...

Page 74: ...eg Ox00al START ACQUISITION Start the ADC sampling WriteReg DevAdr CSR Ox8012 1 5 5 6 Driver Excerpt for DMA Operations The followingi san excerptfrom t h eDASd r i v e r t h a ts e t sup t h e DMAc o...

Page 75: ...xstrategy DMA strategy routine dvxstrategy bp register struct buf bp register struct mb_device md register struct AV25device av register struct AV regs regs register struct ChainBlk cbp register struc...

Page 76: ...ut the FIFO with a reset i regs offset save offset reg j regs4ratediv save rate reg k regsdthresh save threshold reg regs csr AV RESET apply the RESET regsdcst avcontrol reg regs offset i restore the...

Page 77: ...f int addr OxffOOOOOO t ERROR if physical address is than 24 bits av error EINVALIDDMAADDRESS dvxbuf unit b flags B ERROR mbrelse md md hd av mbinfo av busy 0 void splx s iodone dvxbuf unit return set...

Page 78: ...erm cnt load 9516 chain address register regs am9516ptr AM CAR LOW Z i int addr sizeof struct ChainBlk regs am9516dat short i Oxffff addr short unsigned int addr av PreTrigBufSz l 1 set up chain reloa...

Page 79: ...ff ifdef DEBUG printf nDVXstrategy Chain Addr Lo Addr x Dat xn AM CAR_LOW regs am9516 dat endif regs am9516ptr AM CAR UP regs am9516dat short int addr 8 0xffOO I WAIT STATES ifdef DEBUG print nDVXstra...

Page 80: ...AM CMDR if regs thresh AV TRIG SEL start channel 1 chaining regs am9516dat STCHAIN 1 start channel 2 chaining regs am9516dat ST CHAIN 2 start up the converter if the external start mode is NOT selecte...

Page 81: ...gregate Conversionrate 204 8 Ksampls max 8700 409 6 Ksamplsmax 8701 Noise 0 5 LSB 50 pV rms Referred to input over 700 kHz equiv noise bandwidth Differentialcrosstalk 100dB 1 kHz 8700 90 dB 1 kHz 8701...

Page 82: ...ceivedfrom a Master Trigger modulewithin the system External Suppliedby the User Data Dependent Generatedat the occurrence of a predefinedvalue on a monitoredchannel Data Transfer Output coding TwoB c...

Page 83: ...ata transfer rates for the DMA operations are highly dependent upon system configuration and system operation The latency of the VME bus resident memory boards the relative position of the DAS on the...

Page 84: ...e VXlbus Specification Rev 1 4for register based cards It is a class 1 TTL user of the P2 connectorbased local buses A and C A 2 CONNECTOR PIN ASSIGNMENTS A 2 f Analog lnput Connector Jf 12 IInput 2 G...

Page 85: ...OUT BG1IN BG1OUT BG21Nf BG20UT BG31N BG30UF Not Used Not Used Not Used BR3 AM0 AM1 AM2 AM3 GND Not Used Not Used GND IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 lRQ1 Not Used DO8 DO9 D l0 D l1 Dl2 D l3 D l4 Dl5 GND...

Page 86: ...sed Not Used Not Used Not Used Not Used Not Used Not Used Not Used GND 5v Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used GND Not Used Not Used Not Used Not Used Not Used Not U...

Page 87: ...The amount of alteration depends upon a the amount of time that the Hold capacitor was tracking sam pling the signal voltage b the amount of time the Hold capacitor was holding the voltage before the...

Page 88: ...th and 32nd channels in a sequence where the sample time Ts 500 0 ps and the hold time for the channel at 200 kHz sampling rate is Th 5N ps where N the Nth channel in the scan Assume that the voltage...

Page 89: ...for anypurpose other than in connection with the installation operation and maintenance of the equipment describedherein PIN 82 5097 Revision 0 March 1993 NOTE This manual applies to revision 4 and fo...

Page 90: ...3000 F a 508 977 6818 European Sales Centre Analogic Ltd scot House DoncastleRoad Bracknell Berks RG12 8PE England Tel 44 344 860111 Fax 44 344 860478 ANL LOGaC I Thewoddre sour torPrecsron sipid fech...

Page 91: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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