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Summary of Contents for 5094-101

Page 1: ...c c 1 1111111 PERIPHERAL EQUIPMENT DIVISION INSTRUCTION MANUAL MODEL 5094 101 TWO PORT MULTIPLEXER PUBLICATION NO 1802 3...

Page 2: ...SEPTEMBER 1974 DATUM INC 1363 South State College Boulevard Anaheim California 92806 PERIPHERAL EQUIPMENT DIVISION INSTRUCT ION MANUAL MODEL 5094 101 TWO PORT MULTIPLEXER PUBLICATION NO 1802 3...

Page 3: ...er Interface Connectors Operation THEORY OF OPERATION 3 1 3 2 3 3 3 3 1 3 3 2 3 3 3 3 3 4 3 3 5 3 4 3 5 Genera 1 Block Diagram Description Logic Description Cont ro 1 Log i c Data Input Bus Address Bu...

Page 4: ...Sections IV and V respectively contain maintenance information and the reference draw ings 1 2 PURPOSE OF EQUIPMENT The Model 5094 101 Multiplexer allows the connection of two peripheral devices to th...

Page 5: ...NAL DESCRIPTION The Model 5094 101 Multiplexer receives and repowers all the signals to and from the computer and peripheral devices It controls and determines the priority of the cycle steal operatio...

Page 6: ...f the Multi_Plexer to a source of AC power and connection of the computer and peripheral device interface cables 2 2 l Power The Multiplexer operates on 120 230 volt 60 Hz single phase power Connect t...

Page 7: ...er priority device connects to Jl03 2 3 OPERATION If only one device is to be operated the connector for the second device must be left open It makes no difference which connec tor is used for a singl...

Page 8: ...ow the direction of the data flow The sheet numbers shown in each box refer to the sheet numbers of Drawing 76085 where that particular logic is shown The control lines out of the control logic which...

Page 9: ...eceives the 16 bit address words from the two per ipheral devices and gates one of them depending on which is being ser Viced at the time out onto the address bus of the SAC channel 3 3 4 Data Output...

Page 10: ...the logic in terms of high11 and low 2 5 to 5V and OV by examination of the logic symbols without the need to memorize the electrical characteristics NANO NOR AND OR etc of the circuits which most ot...

Page 11: ...Low11 NANO Output is 11 Low11 Output is 11 High11 OR Either A or both Inputs 11High TYPE SP384 INTEGRATED CIRCUIT Output is 11 High Oo Both Inputs Low 3 4 AND Output is Low 1 0 0 NOR Either A Output...

Page 12: ...rcuit can be used as a high input OR or a 11 low11 input AND A 11 low wired OR11 or a high wired AND11 function can also be Implemented with certain integrated circuits by tying the outputs together a...

Page 13: ...Output Goes 11 Low11 114 TO lO LINE DECODER SYMBOL J K Flip Flop sets ff when 1 1ow 1 J enable when 11 high11 Clock upon transition to 11 Jow11 K enable when high resets ff when 11 Jow11 J 9 CL K 3 6...

Page 14: ...Same as Before Clock Low High Reset High Low Set High High Opposite of Be fore Clock As illustrated in the Truth Table the J K flip flop has no forbidden combination for its J and K inputs If both inp...

Page 15: ...the Multiplexer are the drawings in Section V 4 2 I Drawings The drawing complement consists of the following a Top Assembly Drawing 5094 101 b Block Diagram 800526 c Logic Diagrams 76085 d Card Assem...

Page 16: ...on the diagrams by chip location on the card The chip location designation corresponds to the column A through N and row 1 through 6 in which the chip is located on the card The IC chip type can be de...

Page 17: ...of 7 C 76085 7 of 7 C 800918 None SECTION V DRAWINGS Title 1130 Multiplexer Block Diagram Power Supply Assembly Power Supply Schematic Top Assembly 1130 Multiplexer 1130 Multiplexer Control 1t30 Mult...

Page 18: ...SAC DEVICE 1 SAC DEVICE 2 Jl02 I I I I I I 1 LTR DATA INPUT ADORE SS DATA OUTPUT REVISIONS DESCRIPTION I I I I I I I 3llt O Dt T O 1e 1130 SAS 80052G...

Page 19: ...i I l GU 2N371S RE VISIONS LTR DESCRIPTION CAIE c 4...

Page 20: ...IS BRki P N 700533 1 FAR5 CE P J 700535 Z N EA 25 N IRAJJ5F OR EJZ P J 9 l 023 REVISIONS LTR DESCRIPTION c l 170U JTcP W Tf EX rC SE CC PP EZ SVl Fl CE VcAJ SID GMVI FUSc SAMP Rc c11F1E1 o s1 P J V 4...

Page 21: ...ED A ADD 115 VAC lABll IA 6 fU il C 0 JBOJ1UJ I 9 z 7 1 rl ll y _ 1 10 PIN mP AS3 1 N Fl b MP p f Ea D lltD PIN CONN 6 f Mn AMP l tf 1D DETAIL A A P J12 IN CO N 240 lflF HL t i itL FUSE ZAMP 2lOV OR I...

Page 22: ...O1 I I3BO ID 387 I 331 I I 3 01 351 1 1 0o jc I 381 I 0 nl I ltn 1 l232_1 I 35 1 I3B1 I I 3Bl I 1 Bl I j Ol I 35G lE 3Bl I Bl I Jf l I I 351 Q 2Jr I I 381 I IoBl I I 3f 1 Bl l I 87 jH I I 3 1 I 351 I...

Page 23: ...3 V1 C3 N SEfi C S REQ I 2 4 Cl 2 Al 7 5A A Cl I _I SO Pr 10 SLVl 1 9 Fl Z CS l VL 13 I CSLVL2 9 S L 10 IZ 13 5 SE V JI02 C St _V_L_I Jl03 Jr CS L_V_L_Z V7 CSl VLI REVISIONS LTR DESCRIPTION DATE APPR...

Page 24: ...14 A J C0 8Z A7 JO A3 E8 II A3 CZ F Ac A3 A 7 E 7 82 Ai Ct F1 12 I A 3 2 Z 14 88 83 CDllJ J 8 13 BZ CP 81 D3 C1 83 DI e c r DI 88 S J 8 03 C7 A2 B J 1 6 A5 c Fl 5 4 50 11 AZ B O AS G cx1z A Pl CX 7 8...

Page 25: ...l 2 N 1 f r 5 K3 K 4 Mt LZ L5 N6 2 II IZ ez 14 CA8l I 14 0 FS CA82 Ml M4 13 I Pl Mt N5 NB M Pl N8 M Ml M 1 Pt N5 N8 6 5bJJ Kl M9 7 J8 Bl W 1 7 I p4 I 50 11 FZ 10 J8 K I cxze M9 C t3 K7 12 I P4 3 04 3...

Page 26: ...RZ S O Ciiii9 T7 i RZ 18 s R4 S8 Cii8iO R f P8 SS J8 R9 T R9 T4 REVISIONS LTR DESCRIPTION DATE APPROVED 5V 5V k 5V 12 J fOZ J IOZ Er 9 5 3 A1i4 TIO vlO G08 7 103 3 z 79 4 IJ4 P VI T9 sz VI rs f T0 50A...

Page 27: ...IJ JT 4 JQ TZ fj LVL4 F 3 Ax ZO G7 H7 4 1 8 H4 7 J J H7 3 H f J 9 3 7 k 2 50JL II 1 150A 50 JI 10 k5 G 1 PiiEiA G Z CHAIJ u rr I I f f EC 12 L VL 5 K2 GI T I 14 7 AX27 AX32 z I vr E 62 E7 LI 1 Z c 6 Z...

Page 28: ...3 our MS AX35 CK38 IE 14 10 z F N9 M5 e N9 E CX 3 Fw t5V 9 5 RI 10 55 150 n 50A INHl8 T 3 6 CS REQ RI i f j p E9 CHANNGl INT RGQ 4 14 Z 7 s 1 8 I RI CX40 4 E9 5 E9 CX41 rt G 4 5v 15011 150 A H2 II CHA...

Page 29: ...OR co VER 5 0N TO 230 VAC 50 H a l u f IOOOV I SL o TE 3RN C c JUMPER AND RED YEL H lMPt R A KE D C JUMPER 1 s 1 E AR PAN SL c30VAC 50 H FRON r P Nl L 11 0 MUX EL n ORG 1 I BRN GRN Tl 91402 3 C RAV E_...

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