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Analog Devices SHARC ADSP-21367, Manual

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Analog Devices SHARC ADSP-21367 Manual Download Page 39

ADSP-21367/ADSP-21368/ADSP-21369

Rev. D

|

Page 39 of 56

|

November 2008

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it 
should meet setup and hold times with regard to SCLK on the 
output port. The serial data output, SDATA, has a hold time 

and delay specification with regard to SCLK. Note that SCLK 
rising edge is the sampling edge and the falling edge is the 
drive edge. 

Table 37. SRC, Serial Output Port

Parameter

Min

Max Unit

Timing Requirements

t

SRCSFS

1

FS Setup Before SCLK Rising Edge

4

ns 

t

SRCHFS

1

FS Hold After SCLK Rising Edge

5.5

ns 

t

SRCCLKW

Clock Width

(t

CCLK

 × 8) ÷ 2 – 1

ns 

t

SRCCLK

Clock Period

t

CCLK

 × 8

ns 

Switching Characteristics

t

SRCTDD

1

Transmit Data Delay After SCLK Falling Edge

9.9

ns 

t

SRCTDH

1

Transmit Data Hold After SCLK Falling Edge

1

ns 

1

 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 28. SRC Serial Output Port Timing

DAI_P20

-

1

(

S

CLK)

DAI_P20

-

1

(F

S

)

t

S

RC

S

F

S

t

S

RCHF

S

DAI_P20

-

1

(

S

DATA)

t

S

RCTDD

t

S

RCTDH

S

AMPLE EDGE

t

S

RCCLK

t

S

RCCLKW

Summary of Contents for SHARC ADSP-21367

Page 1: ...he SHARC family The ADSP 21367 ADSP 21368 ADSP 21369 are available with a 400 MHz core instruction rate with unique audiocen tric peripherals such as the digital applications interface S PDIF transceiver serial ports 8 channel asynchronous sample rate converter precision clock generators and more For complete ordering information see Ordering Guide on Page 55 Figure 1 Functional Block Diagram SPI ...

Page 2: ...l memory devices Digital applications interface DAI includes eight serial ports four precision clock generators an input data port an S PDIF transceiver an 8 channel asynchronous sample rate converter and a signal routing unit Digital peripheral interface DPI includes three timers two UARTs two SPI ports and a 2 wire interface port Outputs of PCGs C and D can be driven on to DPI pins 8 dual data l...

Page 3: ...nout 48 208 Lead LQFP_EP Pinout 51 Package Dimensions 52 Surface Mount Design 53 Automotive Products 54 Ordering Guide 54 REVISION HISTORY 11 08 Rev C to Rev D Corrected all outstanding document errata Changed digital audio interface to digital applications interface throughout this document This change is a naming convention change only and does not effect the operation or specification of this p...

Page 4: ...nsmitter eight channels asynchronous sample rate converters eight serial ports a 16 bit parallel input port PDAP a flexible signal routing unit DAI SRU Digital peripheral interface that includes three timers a 2 wire interface two UARTs two serial peripheral interfaces SPI and a flexible signal routing unit DPI SRU SHARC FAMILY CORE ARCHITECTURE The ADSP 21367 ADSP 21368 ADSP 21369 are code compat...

Page 5: ...ute a multiply an add and a subtract in both processing elements while branching and fetching up to four 32 bit values from memory all in a single instruction MEMORY ARCHITECTURE The ADSP 21367 ADSP 21368 ADSP 21369 processors add the following architectural features to the SIMD SHARC family core On Chip Memory The processors contain two megabits of internal RAM and six megabits of internal mask p...

Page 6: ...7FFF Block 0 ROM Reserved 0x0010 0000 0x0012 FFFF Reserved 0x0004 F000 0x0004 FFFF Reserved 0x0009 4000 0x0009 FFFF Reserved 0x0009 E000 0x0009 FFFF Reserved 0x0013 C000 0x0013 FFFF Block 0 SRAM 0x0004 C000 0x0004 EFFF Block 0 SRAM 0x0009 0000 0x0009 3FFF Block 0 SRAM 0x0009 8000 0x0009 DFFF Block 0 SRAM 0x0013 0000 0x0013 BFFF Block 1 ROM Reserved 0x0005 0000 0x0005 BFFF Block 1 ROM Reserved 0x00...

Page 7: ...the processors using DMA transfers Other DMA features include interrupt generation upon com pletion of DMA transfers and DMA chaining for automatic linked DMA transfers Delay Line DMA The ADSP 21367 ADSP 21368 ADSP 21369 processors pro vide delay line DMA functionality This allows processor reads and writes to external delay line buffers in external memory SRAM or SDRAM with limited core interacti...

Page 8: ...used to perform synchronous or asyn chronous sample rate conversion across independent stereo channels without using internal processor resources The four SRC blocks can also be configured to operate together to con vert multichannel audio data without phase mismatches Finally the SRC can be used to clean up audio data from jittery clock sources such as the S PDIF receiver Digital Peripheral Inter...

Page 9: ...only once per PWM period This results in PWM patterns that are symmetrical about the midpoint of the PWM period In double update mode a second updating of the PWM registers is implemented at the midpoint of the PWM period In this mode it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3 phase PWM inverters ROM Based Security The ADSP 21367 ADSP 21368 ADSP...

Page 10: ...e programmer can focus on those areas in the program that impact performance and take corrective action Debugging both C C and assembly programs with the VisualDSP debugger programmers can View mixed C C and assembly code interleaved source and object information Insert breakpoints Set conditional breakpoints on registers memory and stacks Perform linear or statistical profiling of program executi...

Page 11: ...esign issues including mechanical layout single processor connections signal buffering signal ter mination and emulator pod logic see the EE 68 Analog Devices JTAG Emulation Technical Reference on the Analog Devices website www analog com use site search on EE 68 This document is updated regularly to keep pace with improvements to emulator support Evaluation Kit Analog Devices offers a range of EZ...

Page 12: ... The DAI SRU provides the connection from the serial ports 8 theSRCmodule theS PDIFmodule inputdataports 2 andtheprecisionclock generators 4 to the DAI_P20 1 pins Pull ups can be disabled via the DAI_PIN_PULLUP register DPI _P14 1 I O with programmable pu2 Pulled high pulled high Digital Peripheral Interface These pins provide the physical interface to the DPI SRU The DPI SRU configuration registe...

Page 13: ...The MS3 0 lines are decoded memory address lines that change at the same time as the other address lines When no external memory access isoccurring theMS3 0 lines areinactive theyare active however whenaconditionalmemoryaccessinstructionisexecuted whetheror not the condition is true TheMS1 pincanbeusedinEPORT FLASHbootmode Seethehardwarereference for more information FLAG 0 IRQ0 I O High Z high Z ...

Page 14: ... Local Clock Out Reset out provides a 4096 cycle delay that allows the PLL to lock This pin can also be configured as a CLKOUT signal to clock synchronous peripherals and memory The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register The default is reset out BR4 1 I O pu 1 Pulled high pulled high External Bus Request Used by the ADSP 213...

Page 15: ...de DATA31 16 DATA15 8 DATA7 0 000 EPDATA32 0 001 FLAGS PWM15 01 EPDATA15 0 010 FLAGS PWM15 01 FLAGS15 8 EPDATA7 0 011 FLAGS PWM15 01 FLAGS15 0 100 PDAP DATA CTRL EPDATA7 0 101 PDAP DATA CTRL FLAGS7 0 110 Reserved 111 Three state all pins 1 These signals can be FLAGS or PWM or a mix of both However they can be selected only in groups of four Their function is determined by the control signals FLAGS...

Page 16: ...H 3 4 High Level Input Current VDDEXT Max VIN VDDEXT Max 10 μA IIL 3 5 6 Low Level Input Current VDDEXT Max VIN 0 V 10 μA IIHPD 5 High Level Input Current Pull Down VDDEXT Max VIN 0 V 250 μA IILPU 4 Low Level Input Current Pull Up VDDEXT Max VIN 0 V 200 μA IOZH 7 8 Three State Leakage Current VDDEXT Max VIN VDDEXT Max 10 μA IOZL 7 9 Three State Leakage Current VDDEXT Max VIN 0 V 10 μA IOZLPU 8 Thr...

Page 17: ...ock the processor uses an internal phase locked loop PLL This PLL based clocking minimizes the skew between the sys tem clock CLKIN signal and the processor s internal clock Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 11 and Table 12 In Table 11 CCLK is defined as fCCLK 2 PLLM fINPUT 2 PLLN where fCCLK CCLK frequency P...

Page 18: ...ching Characteristics specify how the processor changes its signals Circuitry external to the processor must be designed for compatibility with these signal characteristics Switching char acteristics describe what the processor will do in a given circumstance Use switching characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timin...

Page 19: ... Valid VDDINT VDDEXT assumes that the supplies are fully ramped to their 1 2 V rails and 3 3 V rails Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem 2 Assumes a stable CLKIN signal after meeting worst case start up timing of crystal oscillators Refer to your crystal oscillator manufacturer s data sheet for start up tim...

Page 20: ...Ordering Guide on Page 55 Unit Min Max Min Max Min Max Min Max Timing Requirements tCK CLKIN Period 155 5 Applies only for CLK_CFG1 0 00 and default values for PLL control bits in PMCTL 100 17 145 100 185 100 22 55 100 ns tCKL CLKIN Width Low 7 51 45 8 51 45 91 45 11 251 45 ns tCKH CLKIN Width High 7 51 45 8 51 45 91 45 11 251 45 ns tCKRF CLKIN Rise Fall 0 4 V to 2 0 V 3 3 3 3 ns tCCLK 6 6 Any cha...

Page 21: ...se Width Low 4tCK ns tSRST RESET Setup Before CLKIN Low 8 ns 1 Applies after the power up sequence is complete At power up the processor s internal phase locked loop requires no more than 100 μs while RESET is low assuming stable VDD and CLKIN not including start up time of external clock oscillator Figure 8 Reset CLKIN RESET tWRST tSRST Table 16 Interrupts Parameter Min Max Unit Timing Requiremen...

Page 22: ...lation mode Timer signals are routed to the DPI_P14 1 pins through the DPI SRU Therefore the timing specifications provided below are valid at the DPI_P14 1 pins Table 17 Core Timer Parameter Min Max Unit Switching Characteristic tWCTIM CTIMER Pulse Width 4 tPCLK 1 ns Figure 10 Core Timer FLAG3 CTIMER tWCTIM Table 18 Timer PWM_OUT Timing Parameter Min Max Unit Switching Characteristic tPWMO Timer ...

Page 23: ... the DPI_P14 1 pins Pin to Pin Direct Routing DAI and DPI For direct pin connections only for example DAI_PB01_I to DAI_PB02_O Table 19 Timer Width Capture Timing Parameter Min Max Unit Switching Characteristic tPWI Timer Pulse Width 2 tPCLK 2 231 1 tPCLK ns Figure 12 Timer Width Capture Timing DPI_P14 1 TIMER2 0 tPWI Table 20 DAI Pin to Pin Routing Parameter Min Max Unit Timing Requirement tDPIO ...

Page 24: ...tCCLK 8 ns tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input Clock 4 5 ns tHTRIG PCG Trigger Hold After Falling Edge of PCG Input Clock 3 ns Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock 2 5 10 ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2 5 2 5 tPCGIP 10 2 5 tPCGIP ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2 5 ...

Page 25: ...s and the serial peripheral interface SPI See Table 5 on Page 12 for more information on flag use Table 22 Flags Parameter Min Max Unit Timing Requirement tFIPW FLAG3 0 IN Pulse Width 2 tPCLK 3 ns Switching Characteristic tFOPW FLAG3 0 OUT Pulse Width 2 tPCLK 1 5 ns Figure 15 Flags DPI_P14 1 FLAG3 0IN DATA31 0 tFIPW DPI_P14 1 FLAG3 0OUT DATA31 0 tFOPW ...

Page 26: ... Requirements tSSDAT DATA Setup Before SDCLK 500 500 ps tHSDAT DATA Hold After SDCLK 1 23 1 23 ns Switching Characteristics tSDCLK SDCLK Period 7 14 6 0 ns tSDCLKH SDCLK Width High 3 2 6 ns tSDCLKL SDCLK Width Low 3 2 6 ns tDCAD Command ADDR Data Delay After SDCLK2 4 8 4 8 ns tHCAD Command ADDR Data Hold After SDCLK2 1 2 1 2 ns tDSDAT Data Disable After SDCLK 5 3 5 3 ns tENSDAT Data Enable After S...

Page 27: ...racteristics tDSDC Command Disable After CLKIN Rise 2 tPCLK 3 ns tENSDC Command Enable After CLKIN Rise 4 0 ns tDSDCC SDCLK Disable After CLKIN Rise 8 5 ns tENSDCC SDCLK Enable After CLKIN Rise 3 8 ns tDSDCA Address Disable After CLKIN Rise 9 2 ns tENSDCA Address Enable After CLKIN Rise 2 tPCLK 4 4 tPCLK ns Figure 17 SDRAM Interface Enable Disable Timing CLKIN COMMAND SDCLK ADDR tDSDC tDSDCC tDSDC...

Page 28: ...r RD High RH 0 20 ns tDARL Address Selects to RD Low1 tSDCLK 3 3 ns tRW RD Pulse Width W 1 4 ns tRWR RD High to WR RD Low HI tSDCLK 0 8 ns W number of wait states specified in AMICTLx register tSDCLK HI RHC IC RHC number of read hold cycles specified in AMICTLx register tSDCLK IC number of idle cycles specified in AMICTLx register tSDCLK H number of hold cycles specified in AMICTLx register tSDCLK...

Page 29: ...R Low2 tSDCLK 2 7 ns tWW WR Pulse Width W 1 3 ns tDDWH Data Setup Before WR High tSDCLK 3 0 W ns tDWHA Address Hold After WR Deasserted H 0 15 ns tDWHD Data Hold After WR Deasserted H 0 02 ns tWWR WR High to WR RD Low tSDCLK 1 5 H ns tDDWR Data Disable Before RD Low 2tSDCLK 4 11 ns tWDE WR Low to Data Enabled tSDCLK 3 5 ns W number of wait states specified in AMICTLx register tSDCLK H number of ho...

Page 30: ...BRx Table 27 AMI Enable Disable Parameter Min Max Unit Switching Characteristics tENAMIAC Address Control Enable After Clock Rise 4 ns tENAMID Data Enable After Clock Rise tSDCLK 4 ns tDISAMIAC Address Control Disable After Clock Rise 8 7 ns tDISAMID Data Disable After Clock Rise 0 ns Figure 20 AMI Enable Disable CLKIN ADDR WR RD MS1 0 DATA tDISAMIAC tDISAMID tENAMIAC tENAMID ADDR WR RD MS1 0 DATA...

Page 31: ...1368 processors BRx Table 28 Multiprocessor Bus Request Parameter Min Max Unit Timing Requirements tSBRI BRx Setup Before CLKIN High 9 ns tHBRI BRx Hold After CLKIN High 0 5 ns Switching Characteristics tDBRO BRx Delay After CLKIN High 9 ns tHBRO BRx Hold After CLKIN High 1 0 ns Figure 21 Shared Memory Bus Request tHBRI tSBRI CLKIN tDBRO tHBRO BRX OUT BRX IN ...

Page 32: ...ts tSFSE 1 FS Setup Before SCLK Externally Generated FS in Either Transmit or Receive Mode 2 5 2 5 2 5 ns tHFSE 1 FS Hold After SCLK Externally Generated FS in Either Transmit or Receive Mode 2 5 2 5 2 5 ns tSDRE 1 Receive Data Setup Before Receive SCLK 1 9 2 0 2 5 ns tHDRE 1 Receive Data Hold After SCLK 2 5 2 5 2 5 ns tSCLKW SCLK Width tCCLK 8 2 0 5 tCCLK 8 2 0 5 tCCLK 8 2 0 5 ns tSCLK SCLK Perio...

Page 33: ... in Receive Mode 1 0 ns tDDTI 2 Transmit Data Delay After SCLK 3 25 ns tHDTI 2 Transmit Data Hold After SCLK 1 0 ns tSCLKIW 3 Transmit or Receive SCLK Width 2 tPCLK 1 5 2 tPCLK 1 5 ns 1 Referenced to the sample edge 2 Referenced to drive edge 3 Minimum SPORT divisor register value Table 31 Serial Ports Enable and Three State Parameter Min Max Unit Switching Characteristics tDDTEN 1 Data Enable fro...

Page 34: ...ANNEL A B DRIVE SAMPLE DRIVE LATE EXTERNAL TRANSMIT FS EXTERNAL RECEIVE FS WITH MCE 1 MFD 0 1ST BIT 2ND BIT DAI_P20 1 SCLK DAI_P20 1 FS 1ST BIT 2ND BIT tHFSE I tSFSE I tDDTE I tDDTENFS tDDTLFSE tHDTE I tSFSE I tDDTE I tDDTENFS tDDTLFSE tHDTE I DAI_P20 1 DATA CHANNEL A B NOTE SERIAL PORT SIGNALS SCLK FS DATA CHANNEL A B ARE ROUTED TO THE DAI_P20 1 PINS USING THE SRU THE TIMING SPECIFICATIONS PROVID...

Page 35: ...ATA CHANNEL A B tDDTI DRIVE EDGE SAMPLE EDGE DATA TRANSMIT INTERNAL CLOCK tSFSI tHFSI tDFSI tHOFSI tSCLKIW tHDTI NOTE EITHER THE RISING EDGE OR FALLING EDGE OF SCLK EXTERNAL SCLK INTERNAL CAN BE USED AS THE ACTIVE SAMPLING EDGE tDDTE DRIVE EDGE SAMPLE EDGE DATA TRANSMIT EXTERNAL CLOCK tSFSE tHFSE tDFSE tHOFSE tSCLKW tHDTE DAI_P20 1 SCLK DAI_P20 1 FS DAI_P20 1 DATA CHANNEL A B DAI_P20 1 SCLK DAI_P2...

Page 36: ...ming Requirements tSISFS 1 FS Setup Before SCLK Rising Edge 4 ns tSIHFS 1 FS Hold After SCLK Rising Edge 2 5 ns tSISD 1 SDATA Setup Before SCLK Rising Edge 2 5 ns tSIHD 1 SDATA Hold After SCLK Rising Edge 2 5 ns tIDPCLKW Clock Width tCCLK 8 2 1 ns tIDPCLK Clock Period tCCLK 8 ns 1 DATA SCLK FS can come from any of the DAI pins SCLK and FS can also come via PCG or SPORTs PCG s input can be either C...

Page 37: ...in Max Unit Timing Requirements tSPCLKEN 1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2 5 ns tHPCLKEN 1 PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2 5 ns tPDSD 1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3 85 ns tPDHD 1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2 5 ns tPDCLKW Clock Width tCCLK 8 2 3 ns tPDCLK Clock Period tCCLK 8 ns Switching Characteristics tPDHLDD Delay of PDAP Strob...

Page 38: ...216 1 tPCLK 1 5 ns Figure 26 PWM Timing PWM OUTPUTS tPWMW tPWMP Table 36 SRC Serial Input Port Parameter Min Max Unit Timing Requirements tSRCSFS 1 FS Setup Before SCLK Rising Edge 4 ns tSRCHFS 1 FS Hold After SCLK Rising Edge 5 5 ns tSRCSD 1 SDATA Setup Before SCLK Rising Edge 4 ns tSRCHD 1 SDATA Hold After SCLK Rising Edge 5 5 ns tSRCCLKW Clock Width tCCLK 8 2 1 ns tSRCCLK Clock Period tCCLK 8 n...

Page 39: ... Parameter Min Max Unit Timing Requirements tSRCSFS 1 FS Setup Before SCLK Rising Edge 4 ns tSRCHFS 1 FS Hold After SCLK Rising Edge 5 5 ns tSRCCLKW Clock Width tCCLK 8 2 1 ns tSRCCLK Clock Period tCCLK 8 ns Switching Characteristics tSRCTDD 1 Transmit Data Delay After SCLK Falling Edge 9 9 ns tSRCTDH 1 Transmit Data Hold After SCLK Falling Edge 1 ns 1 DATA SCLK and FS can come from any of the DAI...

Page 40: ...default I2 S justified mode LRCLK is low for the left channel and high for the right channel Data is valid on the rising edge of SCLK The MSB is left justified to an LRCLK transition but with a single SCLK period delay Figure 31 shows the left justified mode LRCLK is high for the left channel and low for the right channel Data is valid on the rising edge of SCLK The MSB is left justified to an LRC...

Page 41: ...etup Before SCLK Rising Edge 3 ns tSIHFS 1 FS Hold After SCLK Rising Edge 3 ns tSISD 1 SData Setup Before SCLK Rising Edge 3 ns tSIHD 1 SData Hold After SCLK Rising Edge 3 ns tSISCLKW Clock Width 36 ns tSISCLK Clock Period 80 ns tSITXCLKW Transmit Clock Width 9 ns tSITXCLK Transmit Clock Period 20 ns 1 DATA SCLK and FS can come from any of the DAI pins SCLK and FS can also come via PCG or SPORTs P...

Page 42: ...Receiver Internal Digital PLL Mode Timing Parameter Min Max Unit Switching Characteristics tDFSI LRCLK Delay After SCLK 5 ns tHOFSI LRCLK Hold After SCLK 2 ns tDDTI Transmit Data Delay After SCLK 5 ns tHDTI Transmit Data Hold After SCLK 2 ns tSCLKIW 1 Transmit SCLK Width 40 ns 1 SCLK frequency is 64 FS where FS the frequency of LRCLK Figure 33 S PDIF Receiver Internal Digital PLL Mode Timing DRIVE...

Page 43: ... Cycle 8 tPCLK 2 ns tSPICHM Serial Clock High Period 4 tPCLK 2 ns tSPICLM Serial Clock Low Period 4 tPCLK 2 ns tDDSPIDM SPICLK Edge to Data Out Valid Data Out Delay Time 2 5 ns tHDSPIDM SPICLK Edge to Data Out Not Valid Data Out Hold Time 4 tPCLK 2 ns tSDSCIM FLAG3 0IN SPI Device Select Low to First SPICLK Edge 4 tPCLK 2 ns tHDSM Last SPICLK Edge to FLAG3 0IN High 4 tPCLK 2 ns tSPITDM Sequential T...

Page 44: ...Assertion to Data Out Active SPI2 0 8 ns tDSDHI SPIDS Deassertion to Data High Impedance 0 6 8 ns tDSDHI 1 SPIDS Deassertion to Data High Impedance SPI2 0 8 6 ns tDDSPIDS SPICLK Edge to Data Out Valid Data Out Delay Time 9 5 ns tHDSPIDS SPICLK Edge to Data Out Not Valid Data Out Hold Time 2 tPCLK ns tDSOV SPIDS Assertion to Data Out Valid CPHASE 0 5 tPCLK ns 1 The timing for these parameters appli...

Page 45: ...s Setup Before TCK High 7 ns tHSYS 1 System Inputs Hold After TCK High 18 ns tTRSTW TRST Pulse Width 4tCK ns Switching Characteristics tDTDO TDO Delay from TCK Low 7 ns tDSYS 2 System Outputs Delay After TCK Low tCK 2 7 ns 1 System Inputs AD15 0 SPIDS CLK_CFG1 0 RESET BOOT_CFG1 0 MISO MOSI SPICLK DAI_Px FLAG3 0 2 System Outputs MISO MOSI SPICLK DAI_Px AD15 0 RD WR FLAG3 0 CLKOUT EMU Figure 36 IEEE...

Page 46: ...de the ranges shown for Typi cal Output Delay vs Load Capacitance and Typical Output Rise Time 20 to 80 V Min vs Load Capacitance Figure 37 Typical Drive at Junction Temperature Figure 38 SDCLK1 0 Drive at Junction Temperature SWEEP VDDEXT VOLTAGE V 20 0 3 5 0 5 1 0 1 5 2 0 2 5 3 0 0 40 30 20 40 10 SOURCE V DDEXT CURRENT mA VOL 3 11V 125 C 3 3V 25 C 3 47V 45 C VOH 30 10 3 11V 125 C 3 3V 25 C 3 47V...

Page 47: ...2x 1 4604 LOAD CAPACITANCE pF 8 0 0 100 250 12 4 2 10 6 RISE AND FALL TIMES ns 200 150 50 FALL y 0 0467x 1 6323 y 0 045x 1 524 RISE Figure 43 SDCLK Typical Output Rise Fall Time 20 to 80 VDDEXT Min Figure 44 SDCLK Typical Output Rise Fall Time 20 to 80 VDDEXT Max LOAD CAPACITANCE pF 0 50 100 150 200 250 10 8 6 4 RISE AND FALL TIMES ns 2 0 RISE FALL y 0 0372x 0 228 y 0 0277x 0 369 LOAD CAPACITANCE ...

Page 48: ...quation where TA ambient temperature C Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required This is only applicable when a heat sink is used Values of θJB are provided for package comparison and PCB design considerations The thermal characteristics values pro vided in Table 44 and Table 45 are modeled values 2 W Figure 45 Typical Ou...

Page 49: ...GND A12 DPI9 B12 DPI8 C12 GND D12 VDDEXT A13 DPI7 B13 DPI5 C13 VDDINT D13 VDDINT A14 DPI6 B14 DPI4 C14 GND D14 GND A15 DPI3 B15 DPI1 C15 GND D15 VDDEXT A16 DPI2 B16 RESET C16 VDDINT D16 GND A17 RESETOUT CLKOUT B17 DATA30 C17 VDDINT D17 VDDEXT A18 DATA31 B18 DATA29 C18 VDDINT D18 GND A19 NC B19 DATA28 C19 DATA27 D19 DATA26 A20 NC B20 NC C20 NC RPBA2 D20 DATA24 E01 DAI11 F01 DAI14 G01 DAI15 H01 DAI1...

Page 50: ...DEXT V05 GND W05 ADDR17 Y05 NC BR12 U06 GND V06 GND W06 ADDR16 Y06 NC BR22 U07 VDDEXT V07 GND W07 ADDR15 Y07 XTAL U08 VDDINT V08 VDDINT W08 ADDR14 Y08 CLKIN U09 VDDEXT V09 GND W09 AVDD Y09 NC U10 GND V10 GND W10 AVSS Y10 NC U11 VDDEXT V11 GND W11 ADDR13 Y11 NC BR32 U12 VDDINT V12 VDDINT W12 ADDR12 Y12 NC BR42 U13 VDDEXT V13 VDDEXT W13 ADDR10 Y13 ADDR11 U14 VDDEXT V14 GND W14 ADDR8 Y14 ADDR9 U15 VD...

Page 51: ... Ball BGA_ED Ball Configuration Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 R P N M L K J H G F E D C B A Y W V U T NO CONNECT VDDINT I O SIGNALS GND KEY VDDEXT AVSS AVDD BOTTOM VIEW Figure 48 256 Ball BGA_ED Ball Configuration Top View 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 R P N M L K J H G F E D C B A Y W V U T NO CONNECT VDDINT I O SIGNALS GND KEY VDDEXT AVSS AVD...

Page 52: ... DATA19 59 ADDR4 101 ADDR22 143 DAI11 185 DPI12 18 DATA18 60 ADDR3 102 MS1 144 DAI10 186 DPI11 19 VDDINT 61 ADDR5 103 MS0 145 DAI8 187 DPI10 20 GND 62 GND 104 VDDINT 146 DAI9 188 DPI9 21 DATA17 63 VDDINT 105 VDDINT 147 DAI6 189 DPI8 22 VDDINT 64 GND 106 GND 148 DAI7 190 DPI7 23 GND 65 VDDEXT 107 VDDEXT 149 DAI5 191 VDDEXT 24 VDDINT 66 ADDR6 108 SDCAS 150 VDDEXT 192 GND 25 GND 67 ADDR7 109 SDRAS 15...

Page 53: ... 45 1 40 1 35 7 3 5 0 VIEW A ROTATED 90 CCW 0 27 0 22 0 17 0 75 0 60 0 45 0 50 BSC LEAD PITCH 28 10 28 00 SQ 27 90 30 20 30 00 SQ 29 80 TOP VIEW PINS DOWN BOTTOM VIEW PINS UP EXPOSED PAD 1 52 53 52 53 105 104 105 104 156 208 1 208 157 156 157 PIN 1 1 60 MAX 1 00 REF SEATING PLANE VIEW A 8 890 REF 8 712 REF 25 50 REF NOTE THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS...

Page 54: ...eters 1 27 NOM 1 70 MAX 0 90 0 75 0 60 BALL DIAMETER 0 70 0 60 0 50 1 00 0 80 0 60 0 10 MIN SEATING PLANE 0 20 COPLANARITY 0 25 MIN 4ⴛ TOP VIEW A1 BALL INDICATOR COMPLIES WITH JEDEC STANDARD MO 192 BAL 2 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 R P N M L K J H G F E D C B A Y W V U T BOTTOM VIEW 27 00 BSC SQ 24 13 REF SQ A1 CORNER INDEX AREA DETAIL A DETAIL A Table 48 BGA_ED Data for Use...

Page 55: ...56 Ball BGA_ED BP 256 ADSP 21367BBPZ 2A2 3 40 C to 85 C 333 MHz 2M bit 6M bit 256 Ball BGA_ED BP 256 ADSP 21367KBPZ 3A2 3 0 C to 70 C 400 MHz 2M bit 6M bit 256 Ball BGA_ED BP 256 ADSP 21367KSWZ 1A2 3 0 C to 70 C 266 MHz 2M bit 6M bit 208 Lead LQFP_EP SW 208 1 ADSP 21367KSWZ 2A2 3 0 C to 70 C 333 MHz 2M bit 6M bit 208 Lead LQFP_EP SW 208 1 ADSP 21367KSWZ 4A2 3 0 C to 70 C 350 MHz 2M bit 6M bit 208 ...

Page 56: ... D Page 56 of 56 November 2008 ADSP 21367 ADSP 21368 ADSP 21369 2008 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05267 0 11 08 D ...

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