Analog Devices SHARC ADSP-21367, Manual

Page: 17 / 56

ADSP-21367/ADSP-21368/ADSP-21369
Rev. D | Page 17 of 56 | November 2008
PACKAGE INFORMATION
The information presented in Figure 3 provides details about
the package branding for the ADSP-21367/ADSP-21368/
ADSP-21369 processors. For a complete listing of product avail-
ability, see
Ordering Guide on Page 55 .
ESD CAUTION
MAXIMUM POWER DISSIPATION
See Estimating Power Dissipation for ADSP-21368 SHARC Pro-
cessors (EE-299) for detailed thermal and power information
regarding maximum power dissipation. For information on
package thermal specifications, see
Thermal Characteristics on
Page 48 .
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 10 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TIMING SPECIFICATIONS
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins (see
Table 8 on Page 15 ).
To determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock.
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in
Table 11
and Table 12 .
In Table 11 , CCLK is defined as:
f
CCLK
= (2 × PLLM × f
INPUT
)
÷
(2 × PLLN)
where:
f
CCLK
= CCLK frequency
PLLM = Multiplier value programmed
PLLN = Divider value programmed
Note the definitions of various clock periods shown in Table 12
which are a function of CLKIN and the appropriate ratio con-
trol shown in
Table 11 .
Figure 3. Typical Package Brand
Table 9. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z RoHS Compliant Option
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliant Designation
yyww Date Code
vvvvvv.x n.n
tppZ-cc
S
AD S P-21 3 6x
a
#yyww country_of_origin
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 10. Absolute Maximum Ratings
Parameter Rating
Internal (Core) Supply Voltage (V
DDINT
) –0.3 V to +1.5 V
Analog (PLL) Supply Voltage (A
VDD
) –0.3 V to +1.5 V
External (I/O) Supply Voltage (V
DDEXT
) –0.3 V to +4.6 V
Input Voltage –0.5 V to +3.8 V
Output Voltage Swing –0.5 V to V
DDEXT
+ 0.5 V
Load Capacitance 200 pF
Storage Temperature Range –65
°
C to +150
°
C
Junction Temperature Under Bias 125
°
C
Table 11. ADSP-21368 Clock Generation Operation
Timing
Requirements
Description Calculation
CLKIN Input Clock 1/t
CK
CCLK Core Clock 1/t
CCLK