Analog Devices HSC-ADC-EVALB-DCZ User Manual Download Page 20 | Manualshive

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UG-173

Evaluation Board User Guide

Rev. B | Page 20 of 24

PCB LAYOUT

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HSC-ADC-EVALB-DCZ

Figure 15. Layer 1—Primary Side

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Figure 16. Layer 2—Ground Plane

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Summary of Contents for HSC-ADC-EVALB-DCZ

Page 1: ...he evaluation kit is easy to set up Additional equipment needed includes an Analog Devices high speed ADC evaluation board a signal source and a clock source Once the kit is connected and powered the evaluation is enabled instantly on the PC The HSC ADC EVALB DCZ can be used with single and multi channel ADCs and converters with demultiplexed digital outputs FUNCTIONAL BLOCK DIAGRAM CLOCK INPUT FI...

Page 2: ...d Setup 11 FIFO Schematics and PCB Layout 12 Pin Definitions Assignments 12 Schematics 13 PCB Layout 20 Ordering Information 22 Bill of Materials 22 Related Links 24 REVISION HISTORY 7 10 Rev A to Rev B Document Title Changed from HSC ADC EVALB to UG 173 Universal Changed Connecting to the HSC ADC FPGA 8Z Section to Connecting to the HSC ADC FIFO5 INTZ Section 8 Changes to Connecting to the HSC AD...

Page 3: ...wall outlet at 47 Hz to 63 Hz The other end is a 2 1 mm inner diameter jack that connects to the PCB at J301 Refer to the instructions included in the ADC data sheet at www analog com for more information about the ADC evaluation board s power supply and other requirements 6 Once the cable is connected to both the computer and the FIFO board and power is supplied the USB drivers start to install T...

Page 4: ... dialog box click the Device tab and then click Browse which is the button adjacent to the open box in the dialog window This opens a file browser and displays all of the models found in the default directory c program files adc_analyzer models If no model files are found follow the on screen directions or repeat Step 1 to install the available models If you have saved the models somewhere other t...

Page 5: ...N TO COMPUTER µCONTROLLER CRYSTAL CLOCK 24MHz OFF DURING DATA CAPTURE RESET SWITCH WHEN ENCODE RATE IS INTERRUPTED OPTIONAL SERIAL PORT INTERFACE CONNECTOR OPEN SOLDER MASK ON ALL DATA AND CLOCK LINES FOR EASY PROBING IDT72V283 32k 16 BIT 133MHz FIFO 120 PIN CONNECTOR PARALLEL CMOS INPUTS TIMING ADJUSTMENT JUMPERS IDT72V283 32k 16 BIT 133MHz FIFO 05870 002 Figure 2 FIFO Components Top View ...

Page 6: ...70 003 Figure 3 FIFO Components Bottom View FIFO 4 1 SUPPORTED ADC EVALUATION BOARDS All the evaluation boards that can be used with the high speed ADC FIFO evaluation kit can be found at www analog com FIFO Some evaluation boards may require an adapter between the ADC evaluation board output connector and the FIFO input connector If an adapter is needed send an email to highspeed converters analo...

Page 7: ...allows the clock source for each channel to be CMOS TTL or ECL The clock signals are ac coupled by 0 1 μF capacitors The R312 and R315 potentiometers allow for fine tuning the threshold of the LVDS gates In applications where fine tuning the threshold is critical these potentiometers can be replaced with a higher resistance value to increase the adjustment range Resistors R301 R302 R303 R304 R311 ...

Page 8: ...C AD922xFFA or HSC ADC AD9283FFA adapter board connect the female connector to the ADC evaluation board and then connect the male connector to the FIFO board Next ensure that the HSC ADC AD922xFFA or HSC ADC AD9283FFA adapter board connects to the data lines Row A and Row B of the FIFO board connector as shown in Figure 4 Email highspeed converters analog com for more detailed information about th...

Page 9: ...picture of the FIFO board is displayed for that application providing a visual example of the correct jumper settings Table 4 Jumper Configurations Jumper Single Channel Settings Top 1 Single Channel Settings Default Bottom Demultiplexed Settings Dual Channel Settings Description J303 In In Out Out Position 2 to Position 4 ties write clocks together J304 In In In In Position 1 to Position 2 POS3 i...

Page 10: ...ct enable empty flag of top FIFO U101 to USB MCU 0 Ω resistor J504 Out Out Out Out Not applicable J505 In In In In Connect enable full flag of top FIFO U101 to USB MCU 0 Ω resistor J506 Out Out Out Out Not applicable J602 Out Out Out Out Not applicable J603 In In In In Not applicable 1 Some jumpers can be a 0 Ω resistor instead of a physical jumper This is indicated in in the jumper description co...

Page 11: ...low dropout 3 3 V linear regulator that supplies the proper bias to the entire board When operating the evaluation board in a nondefault condition J316 can be removed to disconnect the switching power supply This enables the user to bias the board independently Use P302 to connect an independent supply to the board A 3 3 V supply is needed with at least a 1 A current capability CONNECTION AND SETU...

Page 12: ...IEW TOP HEAD ON VIEW BOTTOM CHANNEL B CHANNEL A CHANNEL B CHANNEL A SPI CONNECTIONS DIGITAL DATA BIT CONNECTIONS GROUND CONNECTIONS C B A CONNECT ONLY BOTTOM TWO ROWS FOR ADCs THAT DO NOT SUPPORT SPI SPI CONTROL LINES GROUND CONNECTIONS DIGITAL DATA BITS OPTIONAL CONTROL LINES CLOCK LINES Figure 7 FIFO 4 1 Triple Row 120 Pin Input Header ...

Page 13: ...44 46 48 5 51 54 55 58 67 7 9 29 28 17 16 15 13 12 11 10 8 27 26 25 24 22 21 19 18 64 75 72 70 76 68 6 77 73 65 31 32 45 47 49 50 52 53 56 57 34 35 37 38 40 41 42 43 62 63 80 69 71 78 59 66 74 79 61 60 2 1 U101 Q9 E102 E101 OE1 REN1 EF1_TF FF1_TF WEN1 D1_16 D1_17 VCC RCLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q10 Q11 Q13 Q14 Q15 Q16 Q17 MRS WRT_CLK1 Q12 POPULATE WITH PIN SOCKET D1_1 D1_0 D1_3 D1_2 D1_5 D1_4 ...

Page 14: ...D CTRL_B CTRL_B DUT_CLK2 D1_15 D1_14 D1_13 D1_12 D1_11 D1_10 D1_9 D1_8 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 D2_0 D2_0 D2_1 D2_1 D2_2 D2_2 D2_3 D2_3 D2_4 D2_4 D2_5 D2_5 D2_6 D2_6 D2_7 D2_7 D2_8 D2_8 D2_9 D2_9 D2_10 D2_10 D2_11 D2_11 D2_12 D2_12 D2_13 D2_13 D2_14 D2_14 D2_15 D2_15 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 D1_8 D1_9 D1_10 D1_11 D1_12 D1_13 D1_14 D1_15 D1_0 D1_1 DUT_CLK1 CLKB MSB LSB CLKA MSB ...

Page 15: ...D VCC V CC GND GND GND V CC GND 14 20 23 3 30 33 36 39 4 44 46 48 5 51 54 55 58 67 7 9 29 28 17 16 15 13 12 11 10 8 27 26 25 24 22 21 19 18 64 75 72 70 76 68 6 77 73 65 31 32 45 47 49 50 52 53 56 57 34 35 37 38 40 41 42 43 62 63 80 69 71 78 59 66 74 79 61 60 2 1 U201 IDT72V283 TQFP 80 BOTTOM FIFO CHANNEL A Q9 E202 E201 OE2 REN2 EF2 FF2 WEN2 D2_16 D2_17 VCC RCLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q10 Q11 Q...

Page 16: ...P INVERT CLOCK 1 INVERT CLOCK 2 SET 0 1 OR 2 XOR GATE DELAYS CONTROLS TOP FIFO SET 0 1 OR 2 XOR GATE DELAYS CONTROLS BOTTOM FIFO REMOVE JUMPER FOR DUAL CHANNEL CONFIGURATION R302 332Ω FOR COHERENT SAMPLING REMOVE R301 R304 AND SHORT C302 AND C303 PLACE JUMPERS BETWEEN PADS ON TOP SIDE J310 J311 R313 332Ω R312 DNP R311 332Ω C310 0 1µF VCC TOP FIFO BOTTOM FIFO 1 10 11 12 13 14 15 16 17 18 19 2 20 3 ...

Page 17: ... 1 2 7 U403 A MC100EPT23DG WEN1 WEN2 R413 49 9Ω R414 49 9Ω R415 40 2Ω R407 49 9Ω R408 49 9Ω R409 40 2Ω 8 D1 9 D1 R410 49 9Ω R411 49 9Ω R412 40 2Ω R404 49 9Ω R405 49 9Ω R406 40 2Ω R403 DNP R402 DNP R401 20KΩ VCC VCC C401 DNP WENS 4 6 WRT_CLK1 WRT_CLK2 3 U401 B MC100EPT22DG VCC C402 0 1µF C403 0 1µF C404 0 1µF C405 0 1µF J401 J402 DNP J403 J404 DNP J405 J406 DNP CONTROLS TOP FIFO CONTROLS BOTTOM FIF...

Page 18: ...1 1 2 Y501 24MHz Q16 OE1 OE2 CTRL_A CTRL_B CTRL_C CTRL_D 1 2 5 6 4 3 7 8 U503 1 4 2 3 J501 CR502 VCC VCC FF2 EF2 Q17 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 FF_USB VCC USB_VBUS E502 VCC RCLK VCC R504 24 9Ω R502 100kΩ R505 24 9Ω R506 24 9Ω R507 24 9Ω R520 24 9Ω R525 24 9Ω R526 24 9Ω R510 24 9Ω R509 10kΩ R508 10kΩ R511 24 9Ω R512 24 9Ω R513 24 9Ω R514 24 9Ω R516 2kΩ R517 2kΩ R515 24 9Ω...

Page 19: ...2 QL3 QL4 QL5 QL6 QL7 RENEXT VCC C601 0 1µF QL1 QL2 QL5 QL6 QL7 QL4 QL0 9 8 7 68 67 66 65 64 63 62 61 60 6 59 58 57 56 55 54 53 52 51 50 5 49 48 47 46 45 44 43 42 41 40 4 39 38 37 36 35 34 33 32 31 30 3 29 28 27 26 25 24 23 22 21 20 2 19 18 17 16 15 14 13 12 11 10 1 J601 DC9 DC1 DC12 DC14 DC15 DC4 DC5 QL3 WRT_CLK1 EF1_BHB FF1_BHB WEN1 MRS RCLK REN1 DC10 DC11 DC7 DC8 DC2 DC3 DC0 DC6 DC13 DC16 DC17 ...

Page 20: ...UG 173 Evaluation Board User Guide Rev B Page 20 of 24 PCB LAYOUT 05870 015 HSC ADC E VALB DCZ Figure 15 Layer 1 Primary Side 05870 016 Figure 16 Layer 2 Ground Plane ...

Page 21: ...Evaluation Board User Guide UG 173 Rev B Page 21 of 24 05870 017 Figure 17 Layer 3 Power Plane 05870 018 Figure 18 Layer 4 Secondary Side ...

Page 22: ... F 11 1 F301 Fuse 1210 6 0 V 2 2 A trip current resettable fuse Tyco Electronics Raychem NANOSMDC110F 2 12 1 J104 Connector 120 pin female PC mount right angle AMP 5650874 4 13 1 J301 Connector 0 08 PCMT RAPC722 power supply connector Switchcraft Inc RAPC722X 14 1 J303 Connector 4 pin Male straight 100 mil Samtec Inc TSW 110 08 G D 15 4 J304 J305 J314 J315 Connector 3 pin Male straight 100 mil Sam...

Page 23: ...IC 16 IC line receiver quad CMOS National Semiconductor Corporation DS90LV048ATM NOPB 37 1 U302 IC SOIC 14 IC gate exclusive OR quad 2 in Fairchild 74VCX86M 38 1 U401 IC SOIC 8 IC translator DL TTL CMOS PECL ON Semiconductor MC100EPT22DG 39 1 U402 IC 20 TSSOP IC driver clock dual 1 5 diff ON Semiconductor MC100EP29DTG 40 1 U403 IC SOIC 8 IC translator DL LVPECL LVTTL Motorola MC100EPT23DG 41 1 U50...

Page 24: ... The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon disco...

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