UG-173
Evaluation Board User Guide
Rev. B | Page 12 of 24
FIFO SCHEMATICS AND PCB LAYOUT
PIN DEFINITIONS/ASSIGNMENTS
05
87
0
-0
0
7
1
40
HEAD-ON VIEW
(TOP)
HEAD-ON VIEW
(BOTTOM)
CHANNEL B
CHANNEL A
CHANNEL B
CHANNEL A
SPI CONNECTIONS
DIGITAL DATA BIT CONNECTIONS
GROUND CONNECTIONS
C
B
A
CONNECT ONLY
BOTTOM TWO ROWS
FOR ADCs THAT DO
NOT SUPPORT SPI.
SPI CONTROL LINES
GROUND CONNECTIONS
DIGITAL DATA BITS
OPTIONAL CONTROL LINES
CLOCK LINES
Figure 7. FIFO 4.1 Triple Row, 120-Pin Input Header
