Analog Devices EVAL-SSM4567Z, User Manual

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UG-704 EVAL-SSM4567Z User Guide
Rev. 0 | Page 6 of 23
PDM CONTROL MODE
The SSM4567 can boot up in PDM control mode. Powering up,
or resetting, the part while the SEL pin, J12, is tied low places
the part in PDM audio and pattern control mode. In this mode,
several functions are controlled via PDM pattern control. I
2 C
remains available, but registers that are controlled via PDM do
not respond to I
2
C control and the proper state of the part is not
reflected when the registers are read. For full I 2 C control, SEL,
J12, must be tied high, then placed into PDM mode using I 2 C
writes. Refer to the SSM4567 data sheet for more details.
PDM CHANNEL SELECTION
The SSM4567 includes a left/right input select pin,
LR_SEL/ADDR, J9 is used to determine which of the time-
multiplexed input streams is routed to the amplifier when using
PDM pattern control mode. The connection to this pin is via
the jumpers labeled ADDR on the
EVAL-SSM4567Z board. To
select the left input channel, connect LR_SEL/ADDR low. To
select the right channel data, connect LR_SEL/ADDR to
high. At any point during amplifier operation, the logic level
applied to LR_SEL/ADDR may be changed and the output
switches between input streams without audible artifacts.
Aside from your logic level selection, no muting, watermarking
pattern, or synchronizing are necessary to achieve a click/pop
free LR_SEL/ADDR transition.
Table 2. LR_SEL/ADDR Function Descriptions
Device Setting LR_SEL/ADDR Pin Configuration
Right Channel Select High (IOVDD)
Left Channel Select Low (GND)
PCM MODE PIN SETUP AND CONTROL
When the SEL pin is tied to IOVDD, the SSM4567 is set for
PCM mode operation. In this mode, the SSM4567 supports
standalone operation, I
2
C control, or control using commands
sent over the input serial audio/TDM interface. See Figure 9 for
the location of J14, the serial port, and the jumpers associated
with the port. Note that the J20 and J21 jumpers must be
removed when I
2 C communication to the part is desired.
Figure 9. Serial Port and Jumper Location
When the LR_SEL/ADDR pin is pulled up via a 47 kΩ resister
(J9 set high and J13 removed), the IC operates in a standalone
mode with most registers set to their default states.
The state of these several pins can change the functionality of
other pins. The LR_SEL/ADDR pin determines the I
2 C device
address. In standalone and TDM control modes, the SCL and
SDA pins are used to determine the TDM slot used (J20 and
J21). For details, see the data sheet or refer to Table 3.
Table 3. PCM Mode Pin Setup
LR_SEL/ADDR SCL SDA Control Mode I
2
C Control Address TDM Slot
STANDALONE SCL SDA I 2 C 0 1
IOVDD SCL SDA I 2 C 1 2
Open SCL SDA I 2 C 2 3
Pull-Up 0 0 Standalone (TDM interface) NA 1
Pull-Up 0 1 Standalone (TDM interface) NA 2
Pull-Up 1 0 Standalone (TDM interface) NA 3
Pull-Up 1 1 Standalone (TDM interface) NA 4
Pull-Up Boost power down
(active low) Shutdown (active low) Standalone (I
2
S interface) NA NA
Pull-Down 0 0 TDM NA 1
Pull-Down 0 1 TDM NA 2
Pull-Down 1 0 TDM NA 3
Pull-Down 1 1 TDM NA 4
12378-
010