UG-1194
EVAL-ADuM4138EBZ
User Guide
Rev. 0 | Page 6 of 18
Table 3. td_OC Blanking Times
tblank[10:7]
Blanking time (μs)
0000 0
0001 0.4
0010 0.6
0011 0.8
0100 1.0
0101 1.2
0110 1.6
0111 2.0
1000 2.4
1001 2.8
1010 3.2
1011 3.6
1100 4.0
1101 4.4
1110 4.8
1111 6.0
ECC_OFF_OP
If set to 1, when an ECC error is detected, the device enters a
soft shutdown, and a fault is registered. This fault is registered
whether a single or double ECC fault is detected. If set to 0,
ECC faults are still set in the control register (Address 10), but
the part continues to operate without shutting down.
Flyback_V[3:0]
The isolated flyback output voltage can be set by the Flyback_V
bits in the EEPROM. The default code is 0111 (16.00 V target).
Table 4 shows the available output voltages.
Table 4. EEPROM Register Map
Flyback_V[5:2] VDD2
Voltage
Setting
(V)
0000 14.25
0001 14.50
0010 14.75
0011 15.00
0100 15.25
0101 15.50
0110 15.75
0111 (Default)
16.00
1000 16.25
1001 16.50
1010 16.75
1011 17.00
1100 17.25
1101 17.50
1110 17.75
1111 20.00
T_Ramp_OP
Set to 0 to allow the over current reference voltage to vary with
temperature. The current reference varies by 10% across −40°C
to +175°C. Set to 1 to have the overcurrent reference voltage set
to 2 V (typical) regardless of sensed temperature.
PWM_OSC
The PWM_OSC bit controls whether the reported TEMP_OUT
pin pulse-width modulation (PWM) frequency is 10 kHz or
50 kHz. When PWM_OSC is set to 0, the output frequency is
10 kHz (typical). When PWM_OSC is set to 1, the PWM
output frequency is 50 kHz (typical).
CONTROL REGISTER
Table 5. Address 10—Control Register Map
Field Bits
Description
Reserved 23:6
Reserved
ECC2_DBL_ERR
5
ECC Bank 2 double error detected
ECC2_SNG_ERR
4
ECC Bank 2 single error detected
ECC1_DBL_ERR
3
ECC Bank 1 double error detected
ECC1_SNG_ERR
2
ECC Bank 1 single error detected
Prog_Busy 1
Program/busy
bit
Sim_Trim 0
Simulate
trim
ECC2_DBL_ERR
If two errors are detected in the EEPROM stored data, the
ECC2_DBL_ERR bit is set to 1 when read. Two errors are
detectable, but uncorrectable using the ECC employed by the
ADuM4138
. ECC2_DBL_ERR shows that a double error is
detected in the memory banks representing trim performed on
the parts outside of registers affected by the user trim address
and the configuration trim address. A value of 0 means no error
is detected.
ECC2_SNG_ERR
If a single error is detected in the EEPROM stored data, the
ECC2_SNG_ERR bit is set to 1 when read. A single error can be
detected and corrected using the ECC employed by the
ADuM4138
. ECC2_SNG_ERR shows that a single error is
detected in the memory banks representing trim performed on
the parts outside of registers affected by the user trim address
and the configuration trim address. A value of 0 means no error
is detected.
ECC1_DBL_ERR
If two errors are detected in the EEPROM stored data, the
ECC1_DBL_ERR bit is set to 1 when read. Two errors are
detectable, but uncorrectable using the ECC employed by the
ADuM4138
. ECC1_DBL_ERR shows that a double error is
detected in the memory banks representing trim performed on
the parts by the user trim address and the configuration trim
address. A value of 0 means no error is detected.
