EVAL-ADuM4138EBZ
User Guide
UG-1194
Rev. 0 | Page 3 of 18
SETTING UP THE EVALUATION BOARD
The EVAL-ADuM4138EBZ evaluation board comes ready to
display VI+ to gate operation.
LOAD
In the stock configuration, two parallel resistor capacitor (RC)
loads, a 1 Ω resistor (R9 or R25) in series with a 100 nF
capacitor (C9 or C16) can be jumped in via Jumper P4 and/or
Jumper P27.
16
24
5-
0
0
2
Figure 2. Simulated IGBT Gate Loads
Removing the P4 and P27 jumpers removes the RC load. Screw
terminals and TO-264 through-holes are provided on the evalu-
ation board as methods to connect other loads to the
ADuM4138
.
TP7 and TP23 provide test points to show the simulated
internal gate connection within an insulated gate bipolar
transistor (IGBT) module that has an integrated 1 Ω series gate
resistor. By jumping P4 or P27, a single RC load can remain.
POWER CONNECTIONS
In the stock configuration, the only power connections required
are the V
DD1
pin and the GND
1
pin on the
ADuM4138
. Voltages
between 6 V and 25 V are recommended for testing. DC current
limits of approximately 1 A are also recommended for up to
20 kHz operation, although lower current limits are acceptable.
INPUT/OUTPUT CONNECTIONS
The VI+ pin can be driven with any 5 V logic or 3.3 V logic
push pull complementary metal-oxide semiconductor (CMOS)
connection or with an adequate open-drain configuration if the
correct pull-up resistor is used. It is recommended to drive the
VI+ pin with a 50 Ω load capable source. If a jumper is in P26,
the 50 Ω load is connected. (Note that the EVAL-ADuM4138EBZ
comes configured with a jumper installed in P26.) R8 is a 0603
surface mount device (SMD) resistor that allows 50 Ω termination.
If a 50 Ω termination is not used, do not allow the VI+ pin to be
driven by a high-Z signal. When not driven, the VI+ pin can be
brought to a safe state by jumping Pin 2 and Pin 3 of Jumper P5,
which shorts VI+ to GND
1
. If no 50 Ω termination is used, VI+
can be driven high by jumping Pin 1 and Pin 2 of Jumper P5.
Do not jump Pin 1 and Pin 2 of P5 if the P26 jumper is set to
have the 50 Ω termination load present. This configuration
sinks the V5 low dropout (LDO) regulator on the primary side.
USING SPI
The
ADuM4138
evaluation board interfaces easily with the
USB-SDP-CABLEZ
cable. When using the SPI bus, place
jumpers on P18, P19, P20, and P21. Connect the
USB-SDP-
CABLEZ
to P17. The evaluation board has an indexing hole to
ensure proper polarity. If the
USB-SDP-CABLEZ
system is to be
used for SPI communication, refer to the Software Installation
Procedure section for more information.
Alternately, any other SPI system can be tested on the evaluation
board by connecting cables to the right side of the P18, P19,
P20, and P21 jumpers. The pins of the evaluation board are
labeled on the silkscreen.
When programming, it is recommended to have Pin 2 and Pin 3
of Jumper P5 shorted to prevent the VI+ pin from affecting the
transfer of the gate drive signal. This configuration shorts VI+
to GND
1
.
16245-
003
Figure 3. EVAL-ADuM4138EBZ with
USB-SDP-CABLEZ
Connected
STOCK CONFIGURATION FAULT OVERIDES
To present the EVAL-ADuM4138EBZ evaluation board with a
simplified test platform, the evaluation board comes configured
with fault mode overrides that normally do not exist in the
application. These overrides can be removed to evaluate the fault
modes, or the user can leave the overrides on the evaluation board
to disable the fault condition and focus on other parts of the IC.
Desaturation Fault Override
Jumping P3 shorts the desaturation detection blanking capacitor
(C8) to the GND
2
pin, which blocks the desaturation fault from
being detected. Removing the jumper on P3 allows the C8
capacitor to be charged via the precision internal 500 μA
current source if an active IGBT is not connected to the
collector pins on the evaluation board. This configuration
causes a desaturation fault approximately 6 μs after the rising
edge of an input signal on the VI+ pin.
Overcurrent Fault Overrides
P9 and P10 provide a way to connect the OC1 pin and the OC2
pin either high or low. The default configuration is to tie the
overcurrent pins low by connecting Pin 2 and Pin 3 of Jumper
P9 and/or Jumper P10. This connects OC1 to GND
1
and OC2
to GND
2
. If the user want to force an overcurrent fault, connect
Pin 1 and Pin 2 of either P9 or P10 to force the overcurrent fault
to be read as soon as possible. This method is a simplified
approach to seeing the overcurrent blanking time as set by the
EEPROM registers.
