Analog Devices EVAL-AD7730LEB, Technical Notes

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EVAL-AD7730LEB
REV. B –4–
1 18
19 36
Figure 3. SKT2 Pin Configuration
Table III. SKT2 Pin Designations
1 NC No Connect. This pin is not connected on the evaluation board.
2 DIN Serial Data Input. Data applied to this pin is buffered before being applied to the AD7730L's DIN pin. The
serial data applied to the DIN pin is written to the input shift register on the part. Data from this input shift
register is transferred to one of the on-chip registers depending on the register selection bits of the
Communications Register.
3 RESET Reset Input. The signal on this pin is buffered before being applied to the RESET pin of the AD7730L. RESET
is an active low input which resets the control logic, interface logic, calibration coefficients, digital filter and
all on-chip registers to power-on status.
4 CS Chip Select. The signal on this pin is buffered before being applied to the CS pin of the AD7730L. CS is an
active low logic input used to select the AD7730L. With this input hard-wired low, the AD7730L operates in
its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to
select the device in systems with more than one device on the serial bus or as a frame synchronisation signal
in communicating with the AD7730L.
5 SCLK Serial Clock. The signal on this pin is buffered before being applied to the SCLK pin of the AD7730L. An
external serial clock is applied to this input to access serial data from the AD7730L. This serial clock can be
a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a non-
continuous clock with the information being transmitted to the AD7730L in smaller batches of data.
6 SYNC Logic Input. The signal on this pin is buffered before being applied to the SYNC pin of the AD7730L. The
SYNC input allows for synchronisation of the digital filters and analog modulators across a number of
AD7730Ls. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control
logic are reset and the analog modulator is also held in its reset state.
7-8 NC No Connect. These pins are not connected on the evaluation board.
9 DV
DD
Digital Supply Voltage. This provides the supply voltage for IC4, the buffer chip which buffers the output
signals from the AD7730L before they are applied to SKT2.
10 RDY Logic output. This is a buffered version of the signal on the AD7730L's RDY pin. RDY is used as a status output
in both conversion and calibration mode. In conversion mode, a logic low on the RDY output indicates that
a new output word is available from the AD7730L data register. The RDY pin will return high upon completion
of a read operation of a full output word. If no data read has taken place after an output update, the RDY line
will return high prior to the next output update, remain high while the update is taking place and return low
again. This gives an indication of when a read operation should not be initiated to avoid reading from the data
register as it is being updated. In calibration mode, RDY goes high when calibration is initiated and returns
low to indicate that calibration is complete.
11-12 NC No Connect. These pins are not connected on the evaluation board.
13 DOUT Serial Data Output. This is a buffered version of the signal on the AD7730L's DOUT pin. Serial data from the
output shift register on the part is clocked out on this pin. This output shift register contains information from
one of the nine on-chip registers depending on the register selection bits of the Communications Register.
14-18 NC No Connect. These pins are not connected on the evaluation board.
19-30 DGND Ground reference point for digital circuitry. Connects to the DGND plane on the evaluation board.
31-36 NC No Connect. These pins are not connected on the evaluation board.