EVAL-AD7730LEB
REV. B
3
Setup Conditions
Table I shows the position in which all the links are set when
the evaluation board is sent out.
Table I. Initial Link Positions
Link No.
Position Function.
LK1
B
Both links in position B to select the
on-board crystal oscillator as the
master clock for the board.
LK2
A
Normal Operating Mode.
LK3
B
REF IN(-) connected directly to
AGND.
LK4
A
POL pin of AD7730L tied high.
LK5
B
REF IN(+) connected to the AV
DD
.
LK6
IN
ACX
connected to SKT5.
LK7
IN
ACX connected to SKT6.
LK8
IN
SKT8 connected to AIN2(+)/D1.
LK9
IN
SKT7 connected to AIN2(-)/D0.
LK10
IN
SKT3 connected to AIN1(+).
LK11
IN
SKT4 connected to AIN1(-).
Figure 2. SKT1 Pin Configuration
2
4
3
1
5
6
7
8
9
Table II. SKT1 Pin Designations
1
1
SCLK
Serial Clock. The signal on this pin is buffered
before being applied to the SCLK pin of the
AD7730L.
2
RDY
Logic Output. This is a buffered version of the
signal on the AD7730L's
DRDY
pin.
3
CS
Chip Select. The signal on this pin is buffered
before being applied to the
CS
pin of the
AD7730L.
4
RESET
Reset Input. The signal on this pin is buffered
before being applied to the
RESET
pin of the
AD7730L.
5
DIN
Serial Data Input. Data applied to this pin is
buffered before being applied to the AD7730L's
DIN pin.
6
DGND Ground reference point for digital circuitry.
Connects to the DGND plane on the evalua-
tion board.
7
DOUT
Serial Data Output. This is a buffered version
of the signal on the AD7730L's DOUT pin.
8
DV
DD
Digital Supply Voltage. The DV
DD
voltage for the
evaluation board can be supplied via this pin
provided no voltage is applied to the main DV
DD
terminal.
9
SYNC
Logic Input. The signal on this pin is buffered
before being applied to the
SYNC
pin of the
AD7730L.
NOTE
1
An explanation of the AD7730L functions mentioned here is given in Table
III as part of the SKT2 pin designations description.
Link Options (Cont'd)
Link No.
Function
LK11
This link is in series with the AIN1(-) analog input.
With this link in place, the analog input on the SKT4 input is connected directly to the AIN1(-) input on the
part.
This link may be removed so that the input signal at SKT4 can be connected to the component grid for
signal conditioning before being applied to the AIN1(-) input of the AD7730L.
EVALUATION BOARD INTERFACING
Interfacing to the evaluation board is either via a 9-way D-
Type connector, SKT1, or a 36-way Centronics connector,
SKT2. The pinout for the SKT1 connector is given in Figure
1 and its corresponding pin designations are given in Table II.
The pinout for this SKT2 connector is shown in Figure 2 and
its pin designations are given in Table III. The evaluation
board should be powered up before a cable is connected to
either of the connectors.
SKT2 is used to connect the evaluation board to the printer
port (parallel port) of a PC. Connection between the two is
direct via a standard parallel printer port cable. SKT1 is used
to connect the evaluation board to any other system.
Summary of Contents for EVAL-AD7730LEB
Page 7: ...EVAL AD7730LEB REV B 7 Figure 6 Mode Register Screen Figure 5 Program Screen ...
Page 8: ...EVAL AD7730LEB REV B 8 Figure 7 AD7730L Evaluation Board Circuit Diagram ...
Page 10: ...EVAL AD7730LEB REV B 10 Figure 8 Component Layout diagram ...
Page 11: ...EVAL AD7730LEB REV B 11 Figure 9 Component Side Artwork Diagram ...
Page 12: ...EVAL AD7730LEB REV B 12 Figure 10 Solder Side Artwork Diagram ...