Analog Devices EVAL-AD5934EB Preliminary Technical Data Download Page 23

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Preliminary Technical Data

EVAL-AD5934EB

Rev. PrC | Page 23 of 32

The correlation is performed for each integer frequency. If the
resulting correlation of the test phasor with the input sample set
is nonzero, there is signal energy at this frequency. If no energy
is found in a bin, there is no energy at that test frequency.

The DFT implemented by the AD5934 is called a single-point
DFT, meaning that the analysis or correlation frequency in the
MAC core is always at the same frequency as the current output
excitation frequency. Therefore, when the system clock for the
AD5934 is 16 MHz, the sample rate of the ADC is 250 kHz
(16 MHz/4). The DSP core requires 1024 samples to perform the
single-point DFT. If the AD5934 tries to examine excitation
frequencies below ≈1 kHz, the errors introduced by spectral
leakage become very significant and result in erroneous
impedance readings.

If the input signal over the 1024-point sample interval is an
integer, there will be a smooth transition from the end of one
period to the beginning of the next point, as shown in Figure 29. If
this number is not an integer, there will not be a smooth
transition from the end of one period to the beginning of the
next point, as shown in Figure 30. The leakage is a result of the
discontinuities introduced by the DFT, assuming a periodic
input signal like that shown in Figure 30.

In order for the AD5934 to analyze the impedance (Z

UNKNOWN

)

at frequencies lower than ≈1 kHz, it is necessary to scale the
system clock so that the sample rate of the ADC is lower and
causes the 1024 samples required for the single-point DFT to
cover an integer number of periods of the current excitation
frequency.

SAMPLES SPAN ENTIRE EXCITATION PERIOD

SAMPLE

WINDOW

DFT ASSUMES A PERIODIC

SAMPLE SET

Figure 29. Sample Set Spanning the Entire Excitation Period

SAMPLES DO NOT SPAN ENTIRE EXCITATION PERIOD

DFT ASSUMES A PERIODIC

SAMPLE SET

544

Figure 30. Sample Set not Spanning the Entire Excitation Period

Frequently Asked Questions
About Measuring Lower Excitation Frequencies

I want to analyze frequencies in the range between 1 kHz and

10 kHz using the AD5934 with a 16 MHz crystal. Will this work?

This is possible, but you will need to scale the system clock

by using an external clock divider. This reduces the sampling
frequency of the ADC to a value less than 250 kHz (f

SAMPLING

MCLK/64); however, the 1024 sample set will now span the
response signal being analyzed. Note that by scaling the system
clock, you reduce the maximum bandwidth of the sweep.

You can use an additional low power DDS part, such as the
AD9834 (see Figure 31), or an integer N divider, such as the
ADF4001 (see Figure 32), to divide down a system clock signal
before applying it to the external clock pin (MCLK) of the
AD5934.

DDS CORE

(27 BITS)

MCLK

SCLK FSYNC SDA

AD9834*

IOUT

VDD

ADCMP601*

SCL

SDA

ADuC7020*

AD5934*