EVAL-AD5934EB
Preliminary Technical Data
Rev. PrC | Page 22 of 32
For example, a user might want to measure an impedance,
Z
UNKNOWN,
that is known to have a value within the range of 90 Ω
to 110 Ω (that is, a small impedance) over the frequency range
of 30 kHz to 32 kHz. In this case, the user may not be able to
characterize the output series resistance (R
OUT
) directly in the
factory/lab. Therefore, the user may choose to add an extra
amplifier circuit as shown in Figure 28 to the signal path of the
AD5934. The user must ensure that the chosen external
amplifier has a sufficiently low output series resistance over the
bandwidth of interest in comparison with the impedance range
being tested (visit
for an op amp
selection guide). The data sheets of most Analog Devices
amplifiers show the closed loop output impedance vs. frequency
at different amplifier gains to provide an idea of the effect on
output series impedance.
The system settings are as follows:
VDD = 3.3 V
VOUT = 2 V p-p
R2 = 20 kΩ
R1 = 4 kΩ
Gain setting resistor = 500 Ω
Z
UNKNOWN
= 100 Ω
PGA setting = ×1
Choose a ratio of R1/R2 to attenuate the excitation voltage at VOUT.
With the values of R1 = 4 kΩ and R2 = 20 kΩ, the signal is attenu-
ated by 1⁄5 (1/5 of 2 V p-p = 400 mV). The maximum current
flowing through the impedance will be 400 mV/90 Ω = 4.4 mA.
The system is subsequently calibrated at a midpoint frequency
in the sweep using the usual method with a midpoint impedance
value of 100 Ω for the calibration resistor and feedback resistor.
Increasing the value of the I-V gain resistor at the RFB pin
improves the dynamic range of the input signal to the receive
side of the AD5934. For example, by increasing the I-V gain
setting resistor at the RFB pin, the peak-to-peak signal presented to
the ADC input increases from 400 mV (Rfb = 100 Ω) to 2 V p-p
(Rfb = 500 Ω).
The gain factor calculated is for a 100 Ω resistor connected
between VOUT and VIN, assuming the output series resistance
of the external amplifier is small enough to be ignored.
One final important point to note about the biasing of the
circuit shown in Figure 28 is that the receive side of the AD5934
is hard biased about VDD/2 by design. Therefore, to prevent the
output of the external amplifier (attenuated AD5934 range 1
excitation signal) from saturating the receive side amplifiers of
the AD5934, a voltage equal to VDD/2 must be applied to the
noninverting terminal of the external amplifier.
Measuring Lower Excitation Frequencies
The AD5934 has a flexible internal direct digital synthesizer (DDS)
core and DAC, which together generate the excitation signal
used to measure the impedance (Z
UNKNOWN
). The DDS core has a
27-bit phase accumulator, allowing subhertz (<0.1 Hz)
frequency resolution. The output of the phase accumulator is
connected to the input of a read only memory (ROM). The
digital output of the phase accumulator is used to address
individual memory locations in the ROM. The digital contents
of the ROM represent amplitude samples of a single cycle of a
sinusoidal excitation waveform. The content of each address
within the ROM look-up table are in turn passed to the input of
a digital-to-analog converter (DAC) that produces the analog
excitation waveform made available at the VOUT pin. The DDS
core (that is, the phase accumulator and the ROM look-up
table) and the DAC are referenced from a single system clock.
The function of the phase accumulator is to act as a system
clock divider.
The system clock for the AD5934 DDS engine is provided by
the user (that is, the user is required to provide a highly
accurate and stable clock (crystal oscillator) at the external
clock pin (MCLK, Pin 8)). Ensure that Bit D3 in the CONTROL
register (Address 81 hex; see
data sheet) is set (D3 = 1).
The system clock is also used by the internal ADC to digitize
the response signal. The ADC requires 16 clock periods to
perform a single conversion. Therefore, with a maximum
system clock frequency of 16 MHz, the ADC can sample the
response signal with a frequency of 250 kHz (16/64 MHz), that is,
a throughput rate of ≈250 kSPS. The ADC converts 1024 samples
and passes the digital results to the multiply accumulate (MAC)
core for processing. The AD5934 MAC core performs a 1024-
point DFT to determine the peak of the response signal at the
ADC input. The DFT offers many advantages over conventional
peak detection mechanisms, including excellent dc rejection as
well as an averaging of errors and phase information.
The throughput rate of the AD5934 ADC scales with the system
clock. Therefore, lower ADC throughput rates, and hence sampling
frequencies, can be achieved by lowering the system clock.
The conventional DFT assumes a sequence of periodic input
data samples in order to determine the spectral content of the
original continuous signal. In the AD5934, these samples come
from the 12-bit ADC for a user-defined range of signal
frequencies. The conventional DFT correlates the input signal
with a series of test phasor frequencies in order to determine
the fundamental signal frequency and its harmonics. The
frequency of the test phasor is at integer multiples of a
fundamental frequency given by the following formula:
N
f
Frequency
Phasor
Test
S
=
where
f
S
is the sampling frequency of ADC, and
N
is the
number of samples taken (1024).
