ADT7476
Rev. B | Page 13 of 72
SERIAL BUS INTERFACE
Control of the ADT7476 is carried out using the serial system
management bus (SMBus). The ADT7476 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7476 has a 7-bit serial bus address. When the device is
powered up with Pin 13 (PWM3/ADDREN) high, the ADT7476
has a default SMBus address of 0101110 or 0x2E. The read/write
bit must be added to get the 8-bit address. If more than one
ADT7476 is used in a system, each ADT7476 is placed in
ADDR SELECT mode by strapping Pin 13 low on power-up.
The logic state of Pin 14 then determines the device’s SMBus
address. The logic of these pins is sampled on power-up.
The device address is sampled on power-up and latched on the first
valid SMBus transaction, more precisely on the low-to-high
transition at the beginning of the 8th SCL pulse, when the serial
bus address byte matches the selected slave address. The selected
slave address is chosen using the ADDREN pin/ ADDR SELECT
pin. Any attempted changes in the address have no effect after
this.
Table 5. Hardwiring the ADT7476 SMBus Device Address
Pin 13 State
Pin 14
Address
0
Low (10 kΩ to GND)
0101100 (0x2C)
0
High (10 kΩ pull-up)
0101101 (0x2D)
1
Don’t care
0101110 (0x2E)
05
38
2-
01
5
ADT7476
14
ADDRESS = 0x2E
V
CC
ADDR SELECT
13
PWM3/ADDREN
10k
Ω
Figure 14. Default SMBus Address = 0x2E
0
53
82
-01
6
ADT7476
14
ADDRESS = 0x2C
13
10k
Ω
ADDR SELECT
PWM3/ADDREN
Figure 15. SMBus Address = 0x2C (Pin 14 = 0)
05
38
2
-01
7
ADT7476
14
ADDRESS = 0x2D
13
V
CC
10k
Ω
ADDR SELECT
PWM3/ADDREN
Figure 16. SMBus Address = 0x2D (Pin 14 = 1)
05
38
2-
01
8
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
ADT7476
14
13
NC
V
CC
10k
Ω
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7476 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7476 IS PLACED INTO ADDR SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
ADDR SELECT
PWM3/ADDREN
Figure 17. Unpredictable SMBus Address if Pin 13 Is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7476 is used in a system.
The serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus a R/W bit that determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device.
2.
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is a 0, the master writes to
the slave device. If the R/W bit is a 1, the master reads from
the slave device.
3.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period. A low-to-high transition,
when the clock is high, can be interpreted as a stop signal.
The number of data bytes transmitted over the serial bus in
a single read or write operation is limited only by what the
master and slave devices can handle.
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