ADT7476
Rev. B | Page 65 of 72
Table 40. PWMx Minimum Duty Cycle Registers
Register Address
Description
Power-On Default
0x64
R/W
PWM1 minimum duty cycle
0x80 (50% duty cycle)
0x65
R/W
PWM2 minimum duty cycle
0x80 (50% duty cycle)
0x66
R/W
PWM3 minimum duty cycle
0x80 (50% duty cycle)
1
These registers become read-only when the ADT7476 is in automatic fan control mode.
Table 41. Register 0x64, Register 0x65, Register 0x66—PWMx Minimum Duty Cycle Registers (Power-On Default = 0x80;
50% duty cycle)
Bit
Name
Description
[7:0]
PWM duty cycle
R/W
These bits define the PWM
MIN
duty cycle for PWMx.
0x00 = 0% duty cycle (fan off ).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (fan full speed).
1
These registers become read-only when the ADT7476 is in automatic fan control mode.
Table 42. T
MIN
Register Address
Description
Power-On Default
0x67
R/W
Remote 1 temperature T
MIN
0x5A (90°C)
0x68
R/W
Local temperatue T
MIN
0x5A (90°C)
0x69
R/W
Remote 2 temperature T
MIN
0x5A (90°C)
1
These are the T
MIN
registers for each temperature channel. When the temperature measured exceeds T
MIN
, the appropriate fan runs at minimum speed and increases
with temperature according to T
RANGE
.
2
These registers become read-only when the Configuration Register 1 LOCK bit is set. Any subsequent attempts to write to these registers fail.
www.BDTIC.com/ADI