ADXL180
Rev. 0 | Page 44 of 56
V
BP
DATA
CONFIGURATION SPECIFICATION
OVERVIEW
The ADXL180 configuration mode allows access to the user-
programmable nonvolatile configuration registers used to
define the function of the device. The configuration mode is
entered by writing a 16-bit configuration mode enable key code
to the V
BP
pin during Phase 1 of the ADXL180 start-up sequence,
which begins immediately after power is applied to the ADXL180.
The 16-bit configuration mode enable key code is 0x5A5A with
no start or parity bits (see Figure 34). The configuration mode
key is sent LSB first. Note that the configuration mode key code
is 16 bits long and the configuration mode read/write command
data frames are 14 bits long. This helps avoid misinterpretation
of either by the ADXL180.
All configuration mode data sent to the ADXL180, including
the configuration mode enable key code is communicated to
the ADXL180 via voltage modulation of the V
BP
pin with
respect to the V
BN
pin. This signal uses pulse duration modula-
tion to combine the clock and digital data. The clock and data
are encoded as shown in Figure 33.
The ADXL180 acknowledges entering the configuration mode
by transmitting the contents of the CREG2 register. This register
contains the configuration/user data programming bit (CUPRG)
status. This allows the user’s configuration/test system to deter-
mine whether the ADXL180 configuration OTP fuse memory
has been programmed without further communication. If the
configuration mode is not entered within the Phase 1 initializa-
tion time period, the ADXL180 treats the pulses on the V
BP
pin
as synchronization pulses (in synchronous mode) or ignores
them in asynchronous mode.
CLOCK
1
0
TIME
V
CT
1
t
IB
t
IB
t
IB
t
IB
t
IB
t
PGO
t
PG1
t
PG1
t
PG0
0
07
CONFIGURATION MODE ENABLE KEY DATA FRAME (16 BITS)
54
4-
05
5
Figure 33. Configuration Mode Receive Pulse Width Data and Clock Encoding
CONFIGURATION MODE KEY
0
1
0
1
1
0
1
0
TRANSMITTED
FIRST
0
1
0
1
1
0
1
0
07
54
4-
0
56
Figure 34. Configuration Mode Enable Key Code Data Frame
TIME
V
BP
I
BUS
16-BIT CONFIG MODE KEY CODE
18-BIT TRANSMIT DATA:
CREG2
t
tm2
t
tm1
07
54
4
-05
7
Figure 35. Configuration Mode Entry Key Code Sequence
