Analog Devices ADSP-2186 Specification Sheet Download Page 15

ADSP-2186

–15–

REV. 0

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

T

AMB

=

T

CASE

 – (PD x 

θ

CA

)

T

CASE

=

Case Temperature in 

°

C

PD

=

Power Dissipation in W

θ

CA

=

Thermal Resistance (Case-to-Ambient)

θ

JA

=

Thermal Resistance (Junction-to-Ambient)

θ

JC

=

Thermal Resistance (Junction-to-Case)

Package

u

JA

u

JC

u

CA

TQFP

50

°

C/W

2

°

C/W

48

°

C/W

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

×

 V

DD

2

 

×

 f

C = load capacitance, f = output switching frequency.

Example

In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:

Assumptions

• External data memory is accessed every cycle with 50% of the

address pins switching.

• External data memory writes occur every other cycle with

50% of the data pins switching.

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V

DD

 = 5.0 V and t

CK

 = 30 ns.

Total Power Dissipation = P

INT

 + (C 

×

 V

DD

2

 

×

 f)

P

INT

 = internal power dissipation from Power vs. Frequency

graph (Figure 8).

(C 

×

 V

DD

2

 

×

 f) is calculated for each output:

# of
Pins

3

 

C

3

 

V

DD

2

3

f

Address, 

DMS

8

× 

10 pF

× 

5

2

 V

× 

33.3 MHz =  66.6 mW

Data Output, 

WR

9

× 

10 pF

× 

5

2

 V

× 

16.67 MHz = 37.5 mW

RD

1

× 

10 pF

× 

5

2

 V

× 

16.67 MHz =  4.2 mW

CLKOUT

1

× 

10 pF

× 

5

2

 V

× 

33.3 MHz = 

8.3 mW

116.6 mW

Total power dissipation for this example is PINT + 116.6 mW.

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

5

SPECIFICATIONS AT 40MHz ARE PRELIMINARY AT THIS PRINTING.

4

I

DD

 MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

  MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14
  30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

3

TYPICAL POWER DISSIPATION AT 5.0V V

DD

 AND T

A

 = 25

°

C EXCEPT WHERE SPECIFIED.

2

IDLE REFERS TO ADSP-2186 STATE OF OPERATION DURING EXECUTION OF IDLE

 INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

DD

 OR GND.

70

20

65

40

35

30

25

60

55

45

50

POWER (P

IDLE

n

) – mW

1/f

CK

 – MHz

28

42

30

32

34

36

38

40

56mW

 30mW

28mW

 32mW

30mW

 34mW

32mW

61mW

67mW

 IDLE (16)

IDLE (128)

IDLE

85

30

80

55

50

45

40

75

70

60

65

35

POWER (P

IDLE

) – mW

1/f

CK

 – MHz

42

30

32

34

36

38

40

69mW

 76mW

84mW

V

DD

 = 5.5V

56mW

61mW

67mW

V

DD

 = 5.0V

45mW

 49mW

54mW

V

DD

 = 4.5V

1/f

CK

 – MHz

42

30

32

34

36

38

40

450

200

425

300

275

250

225

400

375

325

350

POWER (P

INT

) – mW

175

150

330mW

245mW

175mW

275mW

195mW

325mW

235mW

370mW

V

DD

 = 5.5V

V

DD

 = 5.0V

 V

DD

 = 4.5V

2186 POWER, INTERNAL

1, 3, 4, 5

POWER, IDLE

1, 2, 3, 5

POWER, IDLE 

n MODES

3, 5

430mW

Figure 8. Power vs. Frequency

Summary of Contents for ADSP-2186

Page 1: ...STEM INTERFACE 16 Bit Internal DMA Port for High Speed Access to On Chip Memory Mode Selectable 4 MByte Byte Memory Interface for Storage of Data Tables Program Overlays 8 Bit DMA to Byte Memory for T...

Page 2: ...ort interface This interface pro vides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP 2100 Family EZ ICE s The ADSP 2186 device need not be r...

Page 3: ...ne edge sensitive two level sensitive and three configurable and seven internal interrupts generated by the timer the serial ports SPORTs the Byte DMA port and the power down circuitry There is also a...

Page 4: ...de which allows BDMA operation with full external overlay memory and I O capability or Host Mode which allows IDMA operation with limited external addressing capabilities The operating mode is determi...

Page 5: ...e The IRQE pin is an external edge sensitive interrupt and can be forced and cleared The IRQL0 and IRQL1 pins are external level sensitive interrupts The IFC register is a write only register used to...

Page 6: ...the serial clock rate may be faster than the processor s reduced internal clock rate Under these conditions interrupts must not be generated at a faster rate than can be serviced due to the additiona...

Page 7: ...resets the RESET signal must meet the mini mum pulse width specification tRSP The RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an exte...

Page 8: ...address is generated as shown in Table III Table III DMOVLAY Memory A13 A12 0 0 Internal Not Applicable Not Applicable 1 External 13 LSBs of Address Overlay 1 0 Between 0x2000 and 0x3FFF 2 External 13...

Page 9: ...MOVLAY When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT These accesses continue until the count reaches z...

Page 10: ...e processor to hold off execution while booting continues through the BDMA interface For BDMA accesses while in Host Mode the ad dresses to boot memory must be constructed externally to the ADSP 2186...

Page 11: ...word that can execute in a single instruction cycle The syntax is a superset ADSP 2100 Family assembly lan guage and is completely source and object code compatible with other family members Programs...

Page 12: ...n for some memory access timing requirements and switching characteristics Note If your target does not meet the worst case chip specifica tion for memory access parameters you may not be able to emul...

Page 13: ...e brackets represent preliminary 40 MHz specifications NOTES 1 Bidirectional pins D0 D23 RFS0 RFS1 SCLK0 SCLK1 TFS0 TFS1 A1 A13 PF0 PF7 2 Input only pins RESET BR DR0 DR1 PWD 3 Input only pins CLKIN R...

Page 14: ...not meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals You have no control over this timing circuitry external t...

Page 15: ...52 V 33 3 MHz 66 6 mW Data Output WR 9 10 pF 52 V 16 67 MHz 37 5 mW RD 1 10 pF 52 V 16 67 MHz 4 2 mW CLKOUT 1 10 pF 52 V 33 3 MHz 8 3 mW 116 6 mW Total power dissipation for this example is PINT 116...

Page 16: ...rrent load iL on the output pin It can be approximated by the fol lowing equation tDECAY CL 0 5V iL from which tDIS tMEASURED tDECAY is calculated If multiple pins such as the data bus are dis abled t...

Page 17: ...l Signals Timing Requirements tRSP RESET Width Low1 5 tCK ns tMS Mode Setup Before RESET High 2 ns tMH Mode Setup After RESET High 5 ns NOTES Parameters displayed inside brackets represent preliminary...

Page 18: ...ld requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control ch...

Page 19: ...H xMS RD WR Disable to BGH Low2 0 ns tSEH BGH High to xMS RD WR Enable2 0 ns NOTES xMS PMS DMS CMS IOMS BMS 1 BR is an asynchronous signal If BR meets the setup hold requirements it will be recognized...

Page 20: ...0 ns Switching Characteristics tRP RD Pulse Width 0 5 tCK 5 w ns tCRD CLKOUT High to RD Low 0 25 tCK 5 0 25 tCK 7 ns tASR A0 A13 xMS Setup before RD Low 0 25 tCK 6 ns tRDA A0 A13 xMS Hold after RD Dea...

Page 21: ...S Setup before WR Low 0 25 tCK 6 ns tDDR Data Disable before WR or RD Low 0 25 tCK 7 ns tCWR CLKOUT High to WR Low 0 25 tCK 5 0 25 tCK 7 ns tAW A0 A13 xMS Setup before WR Deasserted 0 75 tCK 9 w ns tW...

Page 22: ...FS RFSOUT Hold after SCLK High 0 ns tRD TFS RFSOUT Delay from SCLK High 15 ns tSCDH DT Hold after SCLK High 0 ns tTDE TFS Alt to DT Enable 0 ns tTDV TFS Alt to DT Valid 14 ns tSCDD SCLK High to DT Dis...

Page 23: ...Address Hold after Address Latch End3 2 ns tIKA IACK Low before Start of Address Latch2 3 0 ns tIALS Start of Write or Read after Address Latch End2 3 3 ns NOTES 1 Start of Address Latch IS Low and I...

Page 24: ...4 5 ns tIDH IAD15 0 Data Hold after End of Write2 3 4 2 ns Switching Characteristics tIKHW Start of Write to IACK High 15 ns NOTES 1 Start of Write IS Low and IWR Low 2 End of Write IS High or IWR Hi...

Page 25: ...ite to IACK Low4 1 5 tCK ns tIKHW Start of Write to IACK High 15 ns NOTES 1 Start of Write IS Low and IWR Low 2 If Write Pulse ends before IACK Low use specifications tIDSU tIDH 3 If Write Pulse ends...

Page 26: ...Disabled after End of Read2 10 ns tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns tIRDV IAD15 0 Previous Data Valid after Start of Read 15 ns tIRDH1 IAD15 0 Previous Data Hold after Star...

Page 27: ...d1 15 ns tIKDH IAD15 0 Data Hold after End of Read2 0 ns tIKDD IAD15 0 Data Disabled after End of Read2 10 ns tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns tIRDV IAD15 0 Previous Data V...

Page 28: ...0 A12 IAD11 A13 IAD12 GND CLKIN XTAL VDD CLKOUT GND VDD WR RD BMS DMS PMS IOMS CMS 71 72 73 74 69 70 67 68 65 66 75 60 61 62 63 58 59 56 57 54 55 64 52 53 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87...

Page 29: ...CLKIN 38 TFS1 63 D6 IRD 88 PF3 14 XTAL 39 RFS1 64 D7 IWR 89 PF2 Mode C 15 VDD 40 DR1 65 D8 90 VDD 16 CLKOUT 41 GND 66 GND 91 PWD 17 GND 42 SCLK1 67 VDD 92 GND 18 VDD 43 ERESET 68 D9 93 PF1 Mode B 19...

Page 30: ...DSP 2186BST 133 40 C to 85 C 33 3 100 Lead TQFP ST 100 ADSP 2186KST 160x 0 C to 70 C 40 0 100 Lead TQFP ST 100 ADSP 2186BST 160x 40 C to 85 C 40 0 100 Lead TQFP ST 100 ST Plastic Thin Quad Flatpack TQ...

Page 31: ...31...

Page 32: ...C2999 6 3 97 PRINTED IN U S A 32...

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