ADSP-21262 EZ-KIT Lite Evaluation System Manual
3-3
EZ-KIT Lite Hardware Reference
The
CLKIN
pin of the DSP connects to a 25 MHz oscillator. The core fre-
quency of the DSP is derived by multiplying the frequency at the
CLKIN
pin by a value determined by the state of the DSP pins,
CLKCFG1
and
CLKCFG0
. The value at these pins is determined by the state of the
SW10
switch (see
“Boot Mode and Clock Ratio Select Switch (SW10)” on
page 3-11
). By default, the EZ-KIT Lite gives a core frequency of 200 MHz.
The
SW10
switch also configures the boot mode of the DSP. The EZ-KIT
Lite is capable of Parallel Port boot and SPI Master Boot. By default, the
EZ-KIT Lite boots from the parallel port. For information about config-
uring the boot modes, see
“Boot Mode and Clock Ratio Select Switch
(SW10)” on page 3-11
.
Parallel Port
The parallel port (PP) of the ADSP-21262 DSP consists of a 16-bit multi-
plex address/data memory bus (
AD15–0
) and an address latch-enable pin
(
ALE
). The interface does not have any memory select pins; these signals
must be generated by decoding the address.
The PP connections to the EZ-KIT Lite are shown in
Figure 3-2
. The PP
is connected to an 8-bit parallel Flash memory, an 8-bit SRAM memory,
and eight general-purpose LEDs. The upper three address bits are con-
nected to a 3-to-8 decoder, providing eight memory select pins. See
“Using External Memory” on page 2-2
for more information about access-
ing the Flash and SDRAM memories.
Because the PP is a multiplexed address/data memory bus, two 8-bit
latches are used to latch the upper address bits. Additional latch is used to
drive the LEDs. The latter allows the LED values to be written to as if
they were at a memory location. For more information about using the
LEDs, refer to the
“Using LEDs and Push Buttons” on page 2-6
.
All of the PP signals are available externally via the expansion interface
connectors (
J3–1
). The pinout of the connectors can be found in
“Sche-
matics” on page B-1
.
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