Analog Devices ADAV4601 System Design Document Download Page 14 | Manualshive

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ADAV4601 System Design Document

Confidential Information

Rev.1 August 2009

Analog Devices

Page 14

TESTPOINTS

Testpoints are distributed on the evaluation board to facilitate the examination of signals. In general a black
testpoint should reference a ground signal, while a red testpoint should reference other (non-ground) signals. Table
5 below indicates the corresponding signal for each testpoint.

Table 5: Testpoints

Testpoint

Signal

TP1

SDIN0

Pin 22 of DUT (Not Stuffed)

TP3

BOARD3.3V

TP6

DUT_DVDD

Output of voltage regulator U35

TP7

DUT_3.3V

DUT_AVDD, DUT_PLLVDD and DUT_ODVDD Supply

TP8

DGND

TP9

DGND

TP10

DGND

TP11

DGND

TP12

DGND

TP13

DGND

TP14

DGND

TP15

MUTEB

Pin 15 of DUT

TP16

SDA

Pin 16 of DUT

TP17

SCL

Pin 17 of DUT

TP18

LRCLK2

Pin 18 of DUT

TP19

BCLK2

Pin 19 of DUT

TP20

DUT_DVDD

Pin 14, 21, 31, 40 and 51 of DUT

TP21

AGND

TP22

VREF

Pin 2 of DUT

TP23

AGND

TP24

AGND

TP25

AGND

TP26

LRCLK0

Pin 26 of DUT (Not Stuffed)

TP27

BCLK0

Pin 27 of DUT (Not Stuffed)

TP29

ADI Testpoint

TP30

ADI Testpoint

TP31

ADI Testpoint

TP32

AGND

TP33

AGND

TP34

AGND

TP35

BCLK1

Pin 35 of DUT (Not Stuffed)

TP36

LRCLK1

Pin 36 of DUT (Not Stuffed)

TP37

SD0

Pin 37 of DUT – I

2

C Address select on reset (Not Stuffed)

TP42

DGND

TP43

DGND

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Summary of Contents for ADAV4601

Page 1: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 1 ADAV4601 System Design Document Rev 1...

Page 2: ...eveloping 23 Connecting the Hardware 24 Installing SigmaStudio 24 Installing Additional DLL Files 24 Evaluating the ADAV4601 using SigmaStudio 26 Powering Up the ADAV4601 Evaluation Board 27 Downloadi...

Page 3: ...ult 0x0E0E 71 Address 0x0104 AUXOUT1 Input Trim Register Default 0x0E0E 71 Address 0x0105 Main Delay Register Default 0x0000 72 Address 0x0106 Automatic Volume Control Default 0x350C 72 Address 0x0107...

Page 4: ...0x8000 91 Address 0x000B Headphone Control Register Default 0x0000 93 Address 0x000C Serial Port Control 2 Register Default 0x8004 93 Address 0x000D Reserved Default 0x0721 94 Address 0x0018 Audio Mut...

Page 5: ...r clicks This power up sequence should be used when the ADAV4601 has been designed into a system Section 3 Programming the ADAV4601 Details the ways in which the ADAV4601 can be programmed and control...

Page 6: ...s i Analog Input f PWM Outputs e ADAV46xx a 96 Way Connector g Headphone Output b SPDIF Out Figure 1 Board Description The ADAV4601 audio processor deals with mixed signals therefore the board is divi...

Page 7: ...ower supply J3 96 way connector J6 PWM Outputs J7 AUXOUT4 Left and Right J8 AUXIN1 Left and Right J10 Headphone 1 Output J12 3 Way Jumper ADAV4601 Clock Select J13 AUXOUT1 Left and Right J18 USB Mini...

Page 8: ...evaluation board PROVIDING A CLOCK SOURCE FOR THE ADAV4601 The ADAV4601 contains a phase locked loop PLL that generates all of the internal clocks required by the ADAV4601 It is possible to set the m...

Page 9: ...tal Y3 MCLK J12 Data from SPDIF asynchronous to MCLK Crystal Y3 MCLK Figure 3 Clocking using the crystal Y3 Once the board has been set up to use crystal Y3 as a clock source the appropriate clock fre...

Page 10: ...ites must be performed to power up and enable the SRCs so as to ensure the correct operation of the device J12 Data from SPDIF asynchronous to MCLK MCLK Data from 96 way asynchronous or synchronous J1...

Page 11: ...tes must be performed to power up and enable the SRCs so as to ensure the correct operation of the device J12 Data from SPDIF asynchronous to MCLK BCLK1 Data from 96 way asynchronous or synchronous J1...

Page 12: ...s due to the fact that the received data is not synchronised to the MCLK of the ADAV4601 and must be re synchronised to the internal processor Please refer to the Appendix A Detailed Register Descript...

Page 13: ...r to Appendix A Detailed Register Descriptionsfor more details on register settings LINK JUMPER CONFIGURATIONS The links jumpers present on the evaluation board are predominantly for in house evaluati...

Page 14: ...t of voltage regulator U35 TP7 DUT_3 3V DUT_AVDD DUT_PLLVDD and DUT_ODVDD Supply TP8 DGND TP9 DGND TP10 DGND TP11 DGND TP12 DGND TP13 DGND TP14 DGND TP15 MUTEB Pin 15 of DUT TP16 SDA Pin 16 of DUT TP1...

Page 15: ...power up sequence from this state is therefore as follows 34 0000 0000 This sets the PLL Frequency to be equal to 512 Fs Given that the sampling frequency is given as 48kHz this means the MCLKI freque...

Page 16: ...ailable DACs on the ADAV4601 In power critical applications or depending on the number of DACs required the user can power up the minimum number of DACs needed for operation 34 000B 2020 This write di...

Page 17: ...re should be a delay of at least 100ms after this write This ensures that the Vref charger has had ample time to charge the Vref voltage from 0V to 1 5V 34 008D 06A0 Once the Vref charger has charged...

Page 18: ...there is a much lower chance of hearing any spurious responses caused by any possible DC level changes while enabling the iDAC It is at this point that the iDAC is connected to the current to voltage...

Page 19: ...C D SRC Un mute Signal D E SRC Input to Flow Valid Data E Valid Data SRC Un mute Signal Delay set by register 0x0082 and 0x0087 Buffer Delay set by register 0x0126 in the default flow SRC Audio Flow S...

Page 20: ...is stored in the audio flow buffer Once the un mute signal for the audio flow has been set the buffer in the audio flow starts outputting valid audio The one requirement for this is to ensure that th...

Page 21: ...0B 2A2A These register writes decrease the gain of the headphone amplifier in steps of 1 5dB from 0dB to 15dB This is an additional precaution to ensure that no pops or clicks are heard at the headpho...

Page 22: ...the Vref buffer to ground and also clamps the headphone outputs to ground It is recommended to wait for 1 second after performing this write to ensure that all residual charge is gone from the Vref c...

Page 23: ...0118h 0120h 011Ah 011Bh 011Ch 011Dh 011Eh 011 Fh 01 21h 0101h 0103h 0121h 0101h 0103h 0121h 0101h 0101h 0104h 0121h 0121h 01 23h SPDIF OUTR SDOR1 SPDIF OUTL SDOL 1 PWM3 LLOW PWM4 RLOW SD OL0 SDOR0 SDI...

Page 24: ...l Converter board to the PC This ensures that the correct driver is loaded for the USB to serial converter INSTALLING SIGMASTUDIO The Installation CD that shipped with the ADAV4601 automatically insta...

Page 25: ...g to Tools Add Ins Browser Figure 17 Add Ins Browser Once selected this opens the Add Ins Browser Window which can be seen underneath The Add Ins Browser is used to include other options in the SigmaS...

Page 26: ...and the second from the asynchronous data input SRC1 These are then connected to a 2 to 1 stereo mux which allows the user to select the input to the audio flow This input is then routed to a single s...

Page 27: ...ADAV4601 To power up the ADAV4601 select File Open and then navigate to the folder in which the SigmaStudio Test Flow is located C Program Files Analog Devices ADAV46xx Documentation Sample Audio Flo...

Page 28: ...has not been programmed correctly Please reset the board and download the power up sequence again Figure 21 SigmaStudio Register Readback DOWNLOADING AND COMPILING AN AUDIO FLOW Once the Audio Flow i...

Page 29: ...simply adjust parameters If you make any changes that require a recompile the status bar will turn blue again CREATING A NEW AUDIO FLOW The previous section explains how to evaluate the ADAV4601 evalu...

Page 30: ...This is provided the USB adaptor board shipped with the evaluation kit is connected to the PC This indicates that the adaptor board is using the correct driver The adaptor board should always be conn...

Page 31: ...ote All input and output pins on each algorithm block must be connected Pins that are left unconnected will cause an error when compiled In order to pass data from the various hardware blocks on the A...

Page 32: ...YNCHRONOUS DIGITAL INPUT 2 CHANNEL SRC ASYNCHRONOUS DIGITAL INPUT SYSTEM CLOCKS PLL SPDIF_IN0 SPDIF_IN1 SPDIF_IN2 SPDIF_IN3 SPDIF_IN4 SPDIF_IN5 SPDIF_IN6 SPDIF_OUT SDO1 SPDIF I O PWM DIGITAL OUTPUT PW...

Page 33: ...mpling frequency Fs of 48kHz When creating audio flows in SigmaStudio it is important to set the sampling frequency of the audio flow to 48kHz This ensures that all filters coefficients are calculated...

Page 34: ...R1 TRIM L R 2 LPF SUB CHANNEL TO INPUT MUXES SUB CHANNEL SDIN0 SDIN1 SPATIALIZER CROSSOVER TRIM DYNAMIC BASS BALANCE LIMITER 0x0126 SDIN3 SRC2 CHANNEL C SRC1 SRC2 CHANNEL A SRC DELAY 0x0127 0x0127 0x0...

Page 35: ...ten can be read back using the Read button This will return the following dialog box Figure 32 Readback ADAV4601 PowerUp Script Note If the dialog box does not display these values the part has not be...

Page 36: ...a comprehensive set of scripts has been supplied with the evaluation kit For example to set the Main Channel Volume on the IC1 IIC Script tab select Open and select the Reg 0114 Main Volume iic file...

Page 37: ...C 3 After 2 5 us time the ADAV4601 will become an I2C master and start reading the EEPROM contents 4 After 1 16 s the ADAV4601 will be finished booting and release I2C bus The ADAV4601 is now an I2C s...

Page 38: ...stream Boot Time The EEPROM has 4 blocks which need to be copied to the part SigmaDSP program 3072 x 6 bytes 18432 bytes SigmaDSP parameters 1024 x 4 bytes 4096 bytes Application layer instructions 6...

Page 39: ...okup table 24567 bytes 6 bytes to set address pointer 24573 bytes clk C I f bytes bits bytes t _ 2 1 1 9 KHz t 390 1 9 24573 1 mS t 07 567 1 Total time for 4 sections 4 3 2 1 t t t t ttotal s ttotal 1...

Page 40: ...A SRC DELAY 0x0127 0x0127 0x0127 0x0127 SRC1 MUTE SRC2 MUTE SRC1 DE EMPHASIS SRC2 DE EMPHASIS SDIN2 SRC2 CHANNEL B 07070 108 Figure 34 Default Audio Flow for the ADAV4601 DEFAULT FLOW STRUCTURE The D...

Page 41: ...nnel after Lip Sync Not Available to Main Mux Main Channel after loudness Not Available to Main Mux Sub Channel Not Available to Main Mux The default for each Mux is no input SCENARIOS The Default Flo...

Page 42: ...N1 to Main 34 0122 FDC1 Enable AVC Lip Sync EQ Bass Loudness Limiter Crossover 34 0121 00C0 Unmute Tweeter and Woofer Digital In I2 S to Digital Out I2S with audio processing 34 0100 3000 Route SDIN0...

Page 43: ...er can be updated in a single I2 C block write Therefore it is recommended that the volume control is updated using the following I2 C write format device address 0114 32 bit data transfer Note that t...

Page 44: ...by multiplying by 223 This simplifies the conversion to Hex that would otherwise be difficult due to the fraction 1 995262315 223 16737473 3 Then simply convert this 5 23 decimal number to Hexadecimal...

Page 45: ...register address in the ADAV4601 that is being written to and DDDD is the data that is being written Default Flow Example Change the low and high frequency of the crossover Address 0x0109 Crossover Re...

Page 46: ...Address 0 Parameter Value 0 00408828258514404 Parameter Data 0X00 0X00 0X85 0XF7 Cell Name Gen Filter1 Parameter Name EQ1940Single11B1 Parameter Address 1 Parameter Value 0 00817668437957764 Parameter...

Page 47: ...ss when the RAM is idle It is recommended to use this method for dynamic updates during run time For example a complete update of one biquad section can occur in one audio frame This method is not ava...

Page 48: ...frequency simply write to address of the register and change it to one of the pre defined cut offs For this example assume the address is 0x1000 and a cut off of 2kHz is assigned to a value of 0xF th...

Page 49: ...tes These zero padded data fields are appended to a 3 byte field consisting of a 7 bit chip address a read write bit and an 16 bit RAM register address The control port knows how many data bytes to ex...

Page 50: ...ontrolled by the SigmaDSP parameters in the Parameter RAM Dealing with this is usually too complex and not easily readable Here is where the Application Layer deals with this complexity offering a sim...

Page 51: ...io Flow the user must generate a number of files from SigmaStudio These files are used by the Application Layer Software Figure 39 Generating and saving files for use in the Application Layer Software...

Page 52: ...Studio project to the Application Layer SigmaStudio Cells Interactive list with all the cells automatically extracted from the SigmaStudio project Cell Parameters Information window with the parameter...

Page 53: ...t step will be importing a SigmaStudio set of files A workspace where the project folder will be created and a project name will be requested Figure 42 New project Open Project Loads a previous projec...

Page 54: ...windows will be populated SigmaStudio Cells and Registers There are some file and version checks behind this function If the GUI doesn t pop up any message and populates the SigmaStudio Cells and Reg...

Page 55: ...params files as shown in the first section and reimport Parameters file is older than program data file Please regenerate params file from SigmaStudio the params params file is older than the program...

Page 56: ...es when programming in C or any other programming language Cell names in SigmaStudio should be given names descriptive of their purpose This makes it easier for the user when creating their Applicatio...

Page 57: ...be added and the destination register This function will call the associated Wizard depending on the detected cell_type The destination register can be either a new register or one previously created...

Page 58: ...he wizard associated with the cell type will be called A single register has a size of 16 bits The wizard will manage the available free bits in the register UNASSIGNED bits When creating a control in...

Page 59: ...Figure 55 Editing a register Delete Register Delete the selected register from the register map The GUI will ask for confirmation before deleting any register Figure 56 Deleting a register Registers...

Page 60: ...ore information about the wizards refer to The Cell Wizards section Figure 57 Editing a cell in a register Register Information This window displays the current status of a register It displays the re...

Page 61: ...er name Name of the register given by the user Bits Number of bits needed by the field this value will depend on the configuration of the cell control Every Wizard will set a default value once a regi...

Page 62: ...a filter shape or type Filter Wizard Gain Control A filter controlled by gain will have all the frequency related parameters fixed Writing to the gain value field the gain response of the filter will...

Page 63: ...hat will define the behaviour of the filter response To do so select the values from the drop menu Figure 63 Multiplexers Wizard This wizard allows control over a mux The Application Layer GUI support...

Page 64: ...and assign the suffixes _LFC and _LLEVEL to generate the two inputs Figure 66 Loudness wizard Clipper Wizard Controls the clipper blocks This wizard is very similar to the volume gain wizard Figure 67...

Page 65: ...eated register if this one was an imported register We provide a set of COD files for the following cell types ADI Surround AVC BBE BBE VIVA BassEnhance Compressor The cod files can be found on the Ap...

Page 66: ...nalog Devices Page 66 Figure 72 Import wizard 2 Figure 73 Import wizard example AVC register created To add or update these cod code files please copy them to this path or install the latest release o...

Page 67: ...Layer Project Creation from SigmaStudio Project The user needs to create a project folder for the Application Layer and then link it to a previously created SigmaStudio project 1 Create a new project...

Page 68: ...mux Source for main channel 0000 0x0 reserved 0x1 ADC1 0x2 reserved 0x3 SDIN0 0x4 SDIN1 0x5 SDIN2 SRC2 Channel B 0x6 SDIN3 SRC2 Channel C 0x7 SRC1 0x8 SRC2 Channel A 0x9 reserved 0xA reserved Bits 11...

Page 69: ...0x4 SDIN1 0x5 SDIN2 SRC2 Channel B 0x6 SDIN3 SRC2 Channel C 0x7 SRC1 0x8 SRC2 Channel A 0x9 reserved 0xA reserved 0xB reserved 0xC delayed main input 0xD main input after loudness 0xE subchannel Bits...

Page 70: ...fault Bits 15 14 Reserved Always write as 0 if writing to this register 00 Bits 13 8 Main input trim These register bits are used to gain or attenuate the input to the main channel processing path fro...

Page 71: ...B 0x1C 14 dB Bits 7 6 Reserved Always write as 0 if writing to this register 00 Bits 5 0 SPDIF input trim These register bits are used to gain or attenuate the input to the SPDIF processing path from...

Page 72: ...ay 0x0002 41 66 s 2 sample delay 0x1C20 150 ms 7200 samples delay Address 0x0106 Automatic Volume Control Default 0x350C Table 15 Bit No Bit Name Description Default Bits 15 12 AVC maximum gain Used t...

Page 73: ...ater than the output level that has been set by these bits the gain is automatically reduced 1100 0x0 18 dBFS 0x1 17 dBFS 0xC 6 dBFS 0xD 5 dBFS 0xE 4 dBFS 0xF 3 dBFS Address 0x0107 Main Sever Band EQ...

Page 74: ...B Address 0x0109 Crossover Register Default 0x0505 Table 18 Bit No Bit Name Description Default Bits 15 14 Reserved Always write as 0 if writing to this register 00 Bits 13 8 Low crossover frequency T...

Page 75: ...0 if writing to this register 00 Bits 13 8 Tweeter trim These register bits are used to gain or attenuate the input to the tweeter outputs from 14 dB to 14 dB in 1 dB steps 001110 0x00 14 dB 0x01 13 d...

Page 76: ...e control words are 28 bit words in twos complement and a 5 23 format This means there are five bits to the left of the decimal point of which the most significant bit is the sign bit To simplify upda...

Page 77: ...ds in twos complement and a 5 23 format This means there are five bits to the left of the decimal point of which the most significant bit is the sign bit Table 23 Bit No Bit Name Description Default B...

Page 78: ...0000 Bits 15 0 Woofer right balance control register 27 0 0x0115 Bits 15 0 main volume Bits 15 0 0000000000000000 Address 0x0116 Tweeter Peak Limiter Control Register Default 0x0F00 This register cont...

Page 79: ...dB s 66 ms 0x0D 140 dB s 62 ms 0x0E 150 dB s 57 ms 0x0F 160 dB s 54 ms 0x10 170 dB s 51 ms 0x11 180 dB s 48 ms 0x12 190 dB s 45 ms 0x13 200 dB s 43 ms 0x14 210 dB s 41 ms 0x15 220 dB s 39 ms 0x16 230...

Page 80: ...4 0 Decay time These register bits control the decay time for the limiter in the range of 10 dB s to 320 dB s in 10 dB s steps 00000 0x00 10 dB s 870 ms 0x01 20 dB s 435 ms 0x02 30 dB s 289 ms 0x03 40...

Page 81: ...dphone 1 AUXOUT4 EQ gain These register bits are used to control the required gain of the equalizer The gain of the equalizer is changed in 0 5 dB steps 001110 0x00 12 dB 0x01 11 5 dB 0x0A 7 dB 0x18 0...

Page 82: ...ontrol register 15 0 0000000000000000 Address 0x011E and Address 0x011F Headphone 1 AUXOUT4 Volume Control Registers Default 0x0080 0x0000 These two registers control the volume for the headphone and...

Page 83: ...4 output Mutes the Headphone 1 and AUXOUT4 output 0 0b mutes 1b unmutes Bit 3 Mute SDO0 output Mutes the SDO0 output 0 0b mutes 1b unmutes Bit 2 Mute SPDIF output Mutes the SPDIF output 0 0b mutes 1b...

Page 84: ...d 1b enabled Bit 6 Enable crossover bypass When set to 1 it enables the crossover low pass and high pass filters for the main channel 0 0b disabled 1b enabled Bit 5 Tweeter output control When set to...

Page 85: ...ese register bits control the frequency of the beeper in the range of 0 Hz beeper off to 11812 5 Hz in 187 5 Hz steps 000101 0x00 0 Hz 0x01 187 5 Hz 0x02 375 Hz 0x03 562 5 Hz 0x04 750 Hz 0x05 937 5 Hz...

Page 86: ...ll mute the output of the SRC It also bypasses de emphasis filters of the SRC Table 38 Bit No Bit Name Description Default Bits 15 6 Reserved Always write as 0 if writing to this register 0000000000 B...

Page 87: ...ample FS 24 576 MHz 01b 256 FS 12 288 MHz 10b 128 FS 6 144 MHz 11b 64 FS 3 072 MHz Bits 8 7 SRC2 Channel A input select Used to select the source for SRC2 channel A 01 00b SDIN0 01b SDIN1 10b SDIN2 11...

Page 88: ...at of the data for SRC1 00 00b I2 S 01b left justified 10b right justified 11b not applicable Bits 6 5 SRC1 word width Use to specify the word width of the data 00 00b 24 bits 01b 20 bits 10b 16 bits...

Page 89: ...o this register 00 Bit 6 AUXDAC3 right Powers on the AUXDAC3 right channel 0 1b block powered up 0b block powered down Bit 5 AUXDAC3 left Powers on the AUXDAC3 left channel 0 1b block powered up 0b bl...

Page 90: ...wered up 0b block powered down Bit 6 S PDIF TX Powers on the S PDIF transmitter 0 1b block powered up 0b block powered down Bit 5 Reserved Always write as 0 if writing to this register 0 Bit 4 SRC2 Po...

Page 91: ...anything other than 000b 00000000 Address 0x000A Misc Control Register Default 0x8000 Table 45 Bit No Bit Name Description Default Bit 15 PWM ready flag read only Indicates the current status of the P...

Page 92: ...s are disabled by default which means that the outputs are at GND When this bit is set to 1 and Bit 14 of this register is set to 1 then the PWM Enable 1 channel is enabled 0 0b disabled 1b enabled Bi...

Page 93: ...t 0x8004 It should be noted that the SDIN3 LRCLK0 BCLK0 LRCLK1 BCLK1 LRCLK2 and BCLK2 can also be used as SPDIF_IN0 SPDIF_IN1 SPDIF_IN2 SPDIF_IN3 SPDIF_IN4 SPDIF_IN5 and SPDIF_IN6 Table 47 Bit No Bit...

Page 94: ...ved Bit 1 8ch TDM enable When set to 1 Time Division Multiplexing mode is enabled 0 0b disabled 1b enabled Bit 0 Reserved Always write as 0 if writing to this register 0 Address 0x000D Reserved Defaul...

Page 95: ...le 49 Bit No Bit Name Description Default Bits 15 4 Reserved Always write as 0 if writing to this register 000000000000 Bit 3 PWM4 status Set when the PWM4 outputs have gone from zero to 50 50 duty cy...

Page 96: ...ed Always write as 0 if writing to this register 000000000 Bit 6 SRC2 Channel C enable Used to enable Channel C of SRC2 0 0b disabled 1b enabled Bits 5 4 SRC2 Channel C Input Select Used to select the...

Page 97: ...rmal mode 1b DAC in low power mode Address 0x008D Reserved Default 0x0220 Address 0x008E SPDIF Transmitter Control 2 Register Default 0x002D Table 53 Bit No Bit Name Description Default Bits 15 8 Rese...

Page 98: ...w RAM Cleared when safe load completed 0 0b finished 1b safe load request Bit 4 Safe load parameter RAM Initiates a safe load to parameter RAM Cleared when safe load completed 0 0b finished 1b safe lo...

Page 99: ...e in the same priority as listed above In addition the 1nF and 100nF ceramic capacitors for the PLL Loop Filter should both be placed as close as possible to the ADAV4601 Note If a ceramic capacitor h...

Page 100: ...1A PWM1B PWM2A PWM2B GROUND PLANE A split ground plane should be used in the layout of the ADAV4601 with the Analog and Digital Grounds connected underneath the ADAV4601 using a single link This is to...

Page 101: ...62 L1 600Z FERRITE BEAD 0805 600Z FEC 1193423 L2 600Z FERRITE BEAD 0805 600Z FEC 1193423 L8 600Z FERRITE BEAD 0805 600Z FEC 1193423 L10 600Z FERRITE BEAD 0805 600Z FEC 1193423 L14 600Z FERRITE BEAD 08...

Page 102: ...r FEC 9402101 C99 2 2uF SMD Capacitor FEC 9402101 C1 10nF CAPACITOR 0603 10NF 25V FEC 3019561 C7 10nF CAPACITOR 0603 10NF 25V FEC 3019561 C15 1nF CAPACITOR 0603 1NF NPO 50V FEC 317202 C9 22nF CAPACITO...

Page 103: ...NECTOR 96 PIN MALE FEC 1097922 J2 SOCKET PCB DC POWER 2 1MM FEC 224 959 PK10 U2 IC SM TRANSMITTER DIGITAL AUDIO FEC 1023448 U19 IC SM RECEIVER DIGITAL AUDIO FEC 1023452 U26 USB Microcontroller Digikey...

Page 104: ...3 OHM 1 10W 5 0603 SMD Digikey P33GCT ND R50 47k RESISTOR 0603 47K FEC 9331255 R28 0R RESISTOR 0603 0R0 FEC 9331662 R41 0R RESISTOR 0603 0R0 FEC 9331662 R46 0R RESISTOR 0603 0R0 FEC 9331662 R47 0R RES...

Page 105: ...100 TP31 TERMINAL PCB RED PK100 FEC 8731144 Pack 100 TP8 TERMINAL PCB BLACK PK100 FEC 8731128 Pack 100 TP9 TERMINAL PCB BLACK PK100 FEC 8731128 Pack 100 TP10 TERMINAL PCB BLACK PK100 FEC 8731128 Pack...

Page 106: ..._READY SPDIF_OUT SPDIF_OUT MCLK_OUT MCLK_OUT 10 F 10nF AUXOUT3L AUXOUT3L 10 F 10nF AUXOUT4R AUXOUT4R XIN XOUT C1 C2 MUTE MUTE SPDIF_IN6 SPDIF_IN6 SPDIF_IN5 SPDIF_IN5 SPDIF_IN4 SPDIF_IN4 SPDIF_IN3 SPDI...

Page 107: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 107 APPENDIX D SCHEMATICS...

Page 108: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 108...

Page 109: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 109...

Page 110: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 110...

Page 111: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 111...

Page 112: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 112...

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