UG-177
Evaluation Board User Guide
Rev. 0 | Page 14 of 27
EVALUATION BOARD SCHEMATICS AND ARTWORK
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AGND
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AI
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15
AI
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16
AI
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CM
17
AI
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3
R
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18
AI
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19
AVD D
20
AGND
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AGND
24
AVD D
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HP
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HP
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26
HP
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27
PD
40
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28
REG
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30
DGN D
31
LR
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32
BC
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DVDD
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EP
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SE
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D
1772_ IO
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RE
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DV
DD
Figure 43. Evaluation Board Schematic—Digital and Analog I/O, Master Clock Generation