background image

REV. 0

EVAL-AD9874EB

–8–

R21

50

A

B

1

2

3

JP23

VDDA

VDDF

TP21

PC

PD

TP22

C98
VAL

C32
VAL

C34
VAL

R51
VAL

C83
0.1

F

CLKN

CLKP

VDDC

IOUTC

VDDQ

VDDD

VDDH

FREF

IOUTL

VDDP

VDDL

LON

LOP

VDDI

SYNCB

FS

DOUTB

DOUTA

11

12

14

6

17

9

13

24

23

1

2

15

5

4

21

16

3

22

18

10

7

8

19

20

39

40

48

27

26

33

25

43

42

38

47

34

37

36

45

32

31

35

30

29

41

44

46

28

CLKOUT

U1

DUT-AD9874

CLKN

CLKP

GCN

GCP

GNDA

GNDC

GNDD

GNDF

GNDQ

GNDS

IF2N

IF2P

IOUTC

MXON

MXOP

PC

PD

RREF

VDDA-ADC

VDDC_CK_SYNTH

VDDF

VDDQ_CK_PUMP

VREFN

VREFP

CLKOUT

CXIF

CXVL

CXVM

DOUTA

DOUTB

FREF

FS

GNDH

GNDI

GNDL

GNDP

GNDT

IFIN

IOUTL

LON

LOP

PE

SYNCB

VDDD_DIGITAL_1

VDDH-DIG.INTERFACE

VDDL-LO

VDDP-LO_PUMP_SUPPLY

VDDI-LNA/MIXER

TP18

VDDH

PE

R23

10k

R43

DNP

VDDH

1

2

3

4

SW2

AGND; 5

TP15

TP16

TP17

TP19

C16

DNP

C26

100nF

C27
1nF

C28

100nF

J2
IF IN

C30
VAL

C31
VAL

C99
VAL

C36

DNP

L1

10UH

NOTE: THESE 5 DEVICES ARE NOT DEFINED (CAPS OR INDUCTORS)

C24
10nF

C60
DNP

+

TP23

TP24

C25

100pF

C23

100pF

R18
100k

C21
DNP

VCM

TP25

R47
0

C15
2.2nF

TP2

TP1

TP11

TP10

C78

100pF

C77

100pF

MXOP

MXON

C43
DNP

C22
180pF

L2

10UH

A

B

1

2

3

JP22

R1

50

VDDI

   

T2

6

S

5

4

P

1

2

3

ADT1-1WT

R2

50

C38

0.1

F

VDDI

J3

MIXER OUTPUT

ADC IN

C37

DNP

Figure 6a. AD9874 Interface

AGND; 3, 4, 5

   

T3

6

S

J6
CLKIN

5

4

P

1

2

3

ADT1-6T

1

2

C62
VAL

C63
VAL

R30
VAL

R31
VAL

A

B

1

2

3

JP18

R33

549

R32

549

TP3

IOUTC

VREGPQ

3

2

3

D5
1SV228

1

D5

1SV228

C29
VAL

C33
VAL

L12

100UH

R3
0

R4
0

CLKP

CLKN

C41

0.01

F

C42

0.01

F

MATCH LENGTH

VOLTAGE CONTROLLED OSCILLATOR

R58

0

R25

100

R26

0

R57

0

R27

0

CLKIN

R52

0

VDDC

CLOCK SYNTHESIZER INTERFACE

AGND; 3, 4, 5

LOIN

   

T1

4

S

J5

5

6

P

3

2

1

ADT1-1WT

1

2

M1

VCOMODULE

35

36

37

38

39

40

41

42

43

44

1

2

3

4

5

6

7

8

9

10

11

12

22

21

20

19

18

17

16

15

14

13

34

33

32

31

30

29

28

27

26

25

24

23

VCOVDD

VIN

CLKOUT

VDD

R62

0

R60

0

R61
200

MATCH LENGTH

R59

0

C65

0.1

F

C64

0.1

F

R63

0

R50
VAL

LON

R48
VAL

LOP

R49
VAL

VDDI

C44
VAL

C66
VAL

C67
VAL

R36
VAL

R37
VAL

HIGH IMPEDANCE

A

B

1

2

3

JP15

R35

549

R34

549

TP4

IOUTL

VREGPQ

LO SYNTHESIZER INTERFACE

Figure 6b. CLK and LO Ext. Input/Synthesizer Interface

Summary of Contents for AD9874

Page 1: ...gain amplifier a band pass analog to digital converter and a decimation filter with programmable decimation factor Auxiliary blocks include clock and LO synthesizers as well as a serial peripheral int...

Page 2: ...R59 R60 Open and R62 0 or a differential signal via transformer T1 with R59 R60 0 and R62 Open The user can supply their own VCO module if the AD9874 s LO synthesizer is to be enabled The VCO module...

Page 3: ...pe cable connector The user is required to purchase a SH68 68 D1 shielded interface cable National Instruments Part No 183432 01 and NI 6533 digital I O card www ni com pdf products us 2mhw332 333e pd...

Page 4: ...ese jumpers TB4 allows the user to apply an unregulated 5 V supply to five voltage regulators that provide regulated supplies to the AD9874 by proper configuration of JP1 JP9 The voltage of these regu...

Page 5: ...74_Eval_SW_090402 vi and click OK Note Analog Devices does not support modifications to any of the VIs contained in the ad9874_eval library Option 2 Loading the run time engine and running executable...

Page 6: ...ibed in Table I of the AD9874 data sheet Note the default values will also appear on the bottom of the control panel display Done Clicking this button closes the AD9874_eval application Read Clicking...

Page 7: ...ile with a time stamp for further evaluation Lastly the display window can be printed to a file or printer using the PRINT PANEL button located in the upper left hand corner Figure 5 Complex Output Si...

Page 8: ...C25 100pF C23 100pF R18 100k C21 DNP VCM TP25 R47 0 C15 2 2nF TP2 TP1 TP11 TP10 C78 100pF C77 100pF MXOP MXON C43 DNP C22 180pF L2 10UH A B 1 2 3 JP22 R1 50 VDDI T2 6 S 5 4 P 1 2 3 ADT1 1WT R2 50 C38...

Page 9: ...U3 XC2S100 R40 0 PD_IN_5V PE_5V PD_OUT_3V _REQ _RESET PC_5V FS SYNCB TDO TCK DONE DOUT U3 XC2S100 55 72 53 70 39 37 38 47 56 63 71 60 67 57 58 59 61 62 64 65 66 68 69 43 50 54 41 42 44 45 46 48 49 51...

Page 10: ...A4 A5 A6 A7 A8 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 VCC G1 G2 VEE 5V R53 1k 5V RCLK WR_CLK _FF _EF _MRS U11 IDT72255LA 59 46 4 30 43 50 49 55 39 33 27 24 5 60 52 48 47 45 44 42 41 40 38 37 36 35 34 32 31 29 28 26...

Page 11: ...INPUTS TB1 1 TB1 2 TB2 1 TB2 2 TP12 C57 10 F 16V TP7 TP35 TP36 TB4 1 TB3 1 TB3 2 TB4 2 D3 5V C75 10 F 16V F1 80MA F2 80MA D4 12V C76 10 F 16V VDIRECT VREGULATED TP13 DOUTB DOUTA 5V DOUT R22 DNP U5 8...

Page 12: ...17 1 F U8 ADP3303A NC 1 2 3 14 13 12 9 6 5 4 8 7 11 10 IN1 IN2 GND OUT1 OUT2 FB SD ERR C71 1 F R29 91k C69 100pF JP17 JP19 R12 50k CW R28 65k VREGHD C70 1 F U9 ADP3303A NC 1 2 3 14 13 12 9 6 5 4 8 7 1...

Reviews: