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REV. 0

–7–

EVAL-AD9874EB

Parameters associated with the Complex FFT display can be
modified by the user. They are highlighted in 

yellow 

across the

top portion of the display window and include CLK rate, FFT
Window type, BW, and FFT averages. BW sets the measurement
bandwidth for which the following parameters are calculated:
signal power, in-band noise power, SNR, SFDR, and NBW.
The Complex FFT display highlights the signal power in 

red

,

the in-band noise power in 

blue,

 and the out-of-band region in

black

. Note, the signal power, SNR, and SFDR results are only

applicable for unmodulated carriers located in FFT bins. The
power of modulated carriers can be measured using the in-band
noise power (

blue

) with the BW parameter set appropriately.

The display window also has the ability to data log the SPI register
settings, the raw I/Q data, and the performance parameters. A
left click over the appropriate Save button will prompt the user
to specify a file name and location for the new data file. The data
is saved into this file with a time stamp for further evaluation.
Lastly, the display window can be printed to a file (or printer) using
the PRINT PANEL button located in the upper left-hand corner.

Figure 5. Complex Output Signal Display with I/Q Constellation

Undecimated Modular Display Description

Figure 5 shows the display that will appear after clicking on the
Observe Undecimated Modulator Output Signal button of the
control panel. The displays show the FFT of the AD9874’s

-

 ADC’s undecimated output data. The clock rate and FFT

window type can be specified in the top right corner of the window.
Note, the FFT display provides a clear demonstration of the
noise-shaping inherent in the band-pass 

-

 ADC’s output

spectrum. Also, the peak signal level reported in the top right
corner of the FFT display is useful in observing the amount of
out-of-band rejection to signals falling outside its pass band
prior to any digital filtering.

This display also provides the quantized output levels with the
ability to write the data to a file. Single SPI register write capa-
bilities are also included with the most current SPI register
settings displayed on the lower portion of the window. A
PRINT PANEL button is also provided on the display.

Summary of Contents for AD9874

Page 1: ...gain amplifier a band pass analog to digital converter and a decimation filter with programmable decimation factor Auxiliary blocks include clock and LO synthesizers as well as a serial peripheral int...

Page 2: ...R59 R60 Open and R62 0 or a differential signal via transformer T1 with R59 R60 0 and R62 Open The user can supply their own VCO module if the AD9874 s LO synthesizer is to be enabled The VCO module...

Page 3: ...pe cable connector The user is required to purchase a SH68 68 D1 shielded interface cable National Instruments Part No 183432 01 and NI 6533 digital I O card www ni com pdf products us 2mhw332 333e pd...

Page 4: ...ese jumpers TB4 allows the user to apply an unregulated 5 V supply to five voltage regulators that provide regulated supplies to the AD9874 by proper configuration of JP1 JP9 The voltage of these regu...

Page 5: ...74_Eval_SW_090402 vi and click OK Note Analog Devices does not support modifications to any of the VIs contained in the ad9874_eval library Option 2 Loading the run time engine and running executable...

Page 6: ...ibed in Table I of the AD9874 data sheet Note the default values will also appear on the bottom of the control panel display Done Clicking this button closes the AD9874_eval application Read Clicking...

Page 7: ...ile with a time stamp for further evaluation Lastly the display window can be printed to a file or printer using the PRINT PANEL button located in the upper left hand corner Figure 5 Complex Output Si...

Page 8: ...C25 100pF C23 100pF R18 100k C21 DNP VCM TP25 R47 0 C15 2 2nF TP2 TP1 TP11 TP10 C78 100pF C77 100pF MXOP MXON C43 DNP C22 180pF L2 10UH A B 1 2 3 JP22 R1 50 VDDI T2 6 S 5 4 P 1 2 3 ADT1 1WT R2 50 C38...

Page 9: ...U3 XC2S100 R40 0 PD_IN_5V PE_5V PD_OUT_3V _REQ _RESET PC_5V FS SYNCB TDO TCK DONE DOUT U3 XC2S100 55 72 53 70 39 37 38 47 56 63 71 60 67 57 58 59 61 62 64 65 66 68 69 43 50 54 41 42 44 45 46 48 49 51...

Page 10: ...A4 A5 A6 A7 A8 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 VCC G1 G2 VEE 5V R53 1k 5V RCLK WR_CLK _FF _EF _MRS U11 IDT72255LA 59 46 4 30 43 50 49 55 39 33 27 24 5 60 52 48 47 45 44 42 41 40 38 37 36 35 34 32 31 29 28 26...

Page 11: ...INPUTS TB1 1 TB1 2 TB2 1 TB2 2 TP12 C57 10 F 16V TP7 TP35 TP36 TB4 1 TB3 1 TB3 2 TB4 2 D3 5V C75 10 F 16V F1 80MA F2 80MA D4 12V C76 10 F 16V VDIRECT VREGULATED TP13 DOUTB DOUTA 5V DOUT R22 DNP U5 8...

Page 12: ...17 1 F U8 ADP3303A NC 1 2 3 14 13 12 9 6 5 4 8 7 11 10 IN1 IN2 GND OUT1 OUT2 FB SD ERR C71 1 F R29 91k C69 100pF JP17 JP19 R12 50k CW R28 65k VREGHD C70 1 F U9 ADP3303A NC 1 2 3 14 13 12 9 6 5 4 8 7 1...

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