background image

UG-075 

Evaluation Board User Guide

 

Rev. 0 | Page 8 of 16 

PLL REFERENCE INPUT WINDOW 

The 

Reference Input Control 

window is shown in Figure 10 

and is accessed by clicking either of the triangular buffer symbols 
immediately to the right of the 

REF 1 (MHz)

 and 

REF 2 (MHz)

 

input reference frequency boxes (see Figure 9). 

0

87

45

-00

6

 

Figure 9. Buffer Symbol 

08

74

5-

0

07

 

Figure 10. Reference Input Control Window 

This window is used to enable the PLL reference inputs, which 
are powered down by default. 

Select 

Enable REF 1

, or 

Enable REF 2

, or both to enable the 

appropriate reference input, and click 

OK

 when finished. If a 

differential input is used, select the 

Use Differential Ref Mode 

(Unchecked = Single-Ended Mode)

 check box. Note that this 

mode should not be used simultaneously with 

Enable REF 1

  

or 

Enable REF 2

.  

The remaining four check boxes control the reference switch-
over modes. If 

Disable Switchover De-Glitch

 is activated, the 

AD951x maintains the phase relationship between the active 
input and PLL output during a reference switchover. Otherwise, 
the AD951x minimizes the phase disturbance at the output 
during a reference switchover.  

 

 

PLL CONFIGURATION WINDOW 

The 

PLL Configuration

 window shown in Figure 11 is opened 

by clicking the 

Config PLL

 button on the main screen. This 

window has three sections: 

SyncB Counter Reset Mode

ReadBack Registers

, and 

Settings

The 

SyncB Counter Reset Mode

 section indicates whether the 

R, A, and B counters are reset when the SYNC pin is activated, and 
controls R0x019[7:6]. See the AD951x data sheet for more 
details.  

The 

ReadBack Registers

 section allows you to see the current 

value of the read-only PLL status register (Address 0x01F). This 
function is very useful for ensuring that the AD951x VCO has 
finished VCO calibration, and that the PLL is locked. 

The 

Settings

 section controls the various PLL settings such as hold-

over. The AD951x data sheet describes these functions in detail. 

Note that the automatic holdover feature should not be enabled 
during VCO calibration.  

08

74

5-

0

08

 

Figure 11. PLL Configuration Window 

REFMON, STATUS, AND LD BUTTONS 

These three blue buttons (

REFMON

STATUS

, and 

LD

) allow 

you to select which signals appear at the REFMON, STATUS,  
and LD pins at Connector P1. Connector P1 is located in the 
center of the evaluation board. The pins in the left column  
of Connector P1 are ground pins, and the ones in the right 
column are signal pins. 

There are many useful diagnostic signals available at these  
pins. The R divider output is particularly useful. In the example 
used in the Quick Start Guide to the AD9516 PLL section, the 
80 kHz signal is visible on the STATUS pin to ensure that the 
reference inputs and R divider are working properly. 

Dynamic signals (such as the R divider output) are primarily 
intended for diagnostics. These diagnostic signals may adversely 
affect PLL performance in critical applications if left on in 
normal operation.  

www.BDTIC.com/ADI

Summary of Contents for AD9516

Page 1: ...16 x AD9517 x and AD9518 x are very low noise PLL clock synthesizers featuring an integrated VCO clock dividers and up to 14 outputs The AD9516 features automatic holdover and a flexible reference inp...

Page 2: ...tware Components 7 Main Window 7 PLL Reference Input Window 8 PLL Configuration Window 8 REFMON STATUS and LD Buttons 8 Register W R Box 9 SYNC PD Power Down and RESET Buttons 9 Reference R Divider Wi...

Page 3: ...damaged SIGNAL CONNECTIONS To connect signals use the following steps 1 Connect a signal generator to the J10 SMA connector By default the reference inputs on this evaluation board are ac coupled and...

Page 4: ...ware Depending on whether the evaluation board was found by the software either light blue text appears in a pop up window indicating that the evaluation board was found or red text appears indicating...

Page 5: ...ox found at the top of the main window see Figure 8 2 Enter the intended reference input frequency in megahertz in the REF 1 MHz box at the upper left corner of the main window 3 Click the triangular...

Page 6: ...is setting normally does not need to be modified 10 Set the VCO divider by clicking the green VCO box in the center of the main window immediately to the left of the Cal VCO button 11 Power down unuse...

Page 7: ...listed in the following sections and each of these has its own window From the main window each functional block can be accessed by clicking that block in the main window When a subwindow closes after...

Page 8: ...The SyncB Counter Reset Mode section indicates whether the R A and B counters are reset when the SYNC pin is activated and controls R0x019 7 6 See the AD951x data sheet for more details The ReadBack...

Page 9: ...e R DIVIDER box on the main window It allows you to set the reference divider If this box is colored gray the PLL is off To turn the PLL on click the PLL MODE box at the top of the main window and sel...

Page 10: ...tter with the 1 3 ns antibacklash pulse width setting Setting the lock detect counter to values greater then 5 PFD cycles can be useful in applications where the loop bandwidth is low and the lock det...

Page 11: ...g However to have the new phase take effect the SYNC signal needs to be toggled by using the SYNC button in the lower left corner of the main window 08745 015 Figure 18 Divider 1 Settings Window LVPEC...

Page 12: ...f delay is shown in the right half of the window The feature is described in detail in the AD951x data sheet 08745 017 08745 018 Figure 22 Output 6 Delay Window DEBUG WINDOW The Debug window shown in...

Page 13: ...w allows you to select which evaluation board the software is controlling Click Refresh List to detect a recently connected evaluation board see Figure 25 08745 020 Figure 25 Select USB Device Window...

Page 14: ...Ethernet line cards as well as applications where the reference clock is relatively high jitter the low loop BW loop filter shown in Table 3 is a better choice It has a flat transfer function with pe...

Page 15: ...reference clock is noisy or for cases where the frequency planning requires a phase detector frequency of 1 MHz or lower Table 3 AD9516 Evaluation Board Low Loop Bandwidth Clock Cleanup Filter Compon...

Page 16: ...of evaluation boards Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of pa...

Reviews: