Analog Devices AD9516, User Manual

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UG-075 Evaluation Board User Guide
Rev. 0 | Page 14 of 16
AD9516 PLL LOOP FILTER
The AD9516 PLL requires an external loop filter whose compo-
nents are tailored for different applications. The third-order
passive configuration shown in Figure 27 usually offers the best
performance and is the one found on the evaluation board.
LF
VCO
CHARGE
PUMP
CP
BYPASS
C1 C2 C3
R1
R2
C
BP
= 220nF
AD9516
08
745
-02
2
Figure 27. PLL Loop Filter
The default loop filter on the AD9516 evaluation board is
optimized for clock generation where the input reference is
relatively quiet. It has a transfer function with slight peaking
(<3 dB) and loop bandwidths from 75 kHz to 200 kHz. In
most of these applications, the phase detector is run at 10 MHz
to 50 MHz. Table 2 shows the correspondence between the
component numbers shown in Figure 27 and those on the
evaluation board, as well as the default values for each version
of the evaluation board. The Quick Start Guide to the AD9516
PLL section uses these default values. The phase detector
frequency is 10 MHz, and the charge pump current for this
example is 3.0 mA. The resulting loop bandwidth is 75 kHz
with 50 degrees of phase margin.
When using this loop filter, the same PLL loop dynamics
can be maintained with a higher input reference frequency
by proportionately reducing the charge pump current, or by
increasing the R divider such that the PFD frequency remains
the same.
For SONET and Ethernet line cards, as well as applications
where the reference clock is relatively high jitter, the low loop
BW loop filter shown in Table 3 is a better choice. It has a flat
transfer function with peaking <0.1 dB and loop bandwidths
from 0.5 kHz to 10 kHz. In most of these applications, the phase
detector should be run at 1 MHz or less. A loop filter design
such as this optimal for hitless reference clock switching.
The user should not consider the previous recommendations as
a substitute for using ADIsimCLK™ to determine the best loop
filter for a given application. ADIsimCLK is a free program that
can help with the design and exploration of the capabilities and
features of the AD9516, including the design of the PLL loop
filter. The website has three sample ADIsimCLK files that include
the AD9516/AD9517/AD9518 default loop filter titled:
AD9516EvalBoardExample_200MHz.clk
AD9517EvalBoardExample_200MHz.clk
AD9518EvalBoardExample_200MHz.clk
ADIsimCLK includes support for the AD9516. The AD9516,
AD9517, and AD9518 share the same loop dynamics.
ADIsimCLK is available at
www.analog.com/clocks .
Table 2. AD9516 Default Loop Filter Values and PLL Setup
ADISimCLK Naming Evaluation Board Location AD9516-0/AD9516-2/AD9516-4 AD9516-1 AD9516-3
C1 C25 470 pF 470 pF 560 pF
R1 R5 910 Ω 820 Ω 750 Ω
C2 C22 8.2 nF 8.2 nF 10 nF
R2 R2 2.4 kΩ 2.4 kΩ 2 kΩ
C3 C31 150 pF 150 pF 180 pF
Input Frequency N/A 10 MHz 10 MHz 10 MHz
R Divider N/A 1 1 1
PFD N/A 10 MHz 10 MHz 10 MHz
N Divider N/A −0: 280
−2: 220
−4: 160 250 200
VCO Frequency N/A −0: 2800 MHz
−2: 2200 MHz
−4: 1600 MHz 2500 MHz 2000 MHz
ICP N/A 3.0 mA 3.0 mA 3.0 mA
www.BDTIC.com/ADI