Analog Devices AD9273, Manual

Page: 9 / 49

AD9273
Rev. B | Page 8 of 48
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
IN
= 5 MHz, full temperature, unless otherwise noted.
Table 2.
Parameter 1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO)
3
Logic 1 Voltage (I
OH
= 800 μA) Full 1.79 V
Logic 0 Voltage (I
OL
= 50 μA) Full 0.05 V
DIGITAL OUTPUTS (DOUTx+, DOUTx−) IN ANSI-644 MODE
1
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 247 454 mV
Output Offset Voltage (V
OS
) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx−) WITH
LOW POWER, REDUCED-SIGNAL OPTION
1
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 150 250 mV
Output Offset Voltage (V
OS
) Full 1.10 1.30 V
Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation , for a complete set of definitions and how these tests were completed.
2
Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.