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AD9273

Rev. B | Page 46 of 48

NOTES

Summary of Contents for AD9273

Page 1: ...ng ultrasound Automotive radar GENERAL DESCRIPTION The AD9273 is designed for low cost low power small size and ease of use It contains eight channels of a low noise preamplifier LNA with a variable g...

Page 2: ...ENCE MATERIALS Press Industry s First Octal Ultrasound Receiver with Digital I Q Demodulator and Decimation Filter Reduces Processor Overhead in Ultrasound Systems Low Cost Octal Ultrasound Receiver w...

Page 3: ...hanges to Features and General Description Sections 1 Changes to Product Highlights Section 3 Changes to Full Channel TGC Characteristics Parameter Table 1 4 Changes to Gain Control Interface Paramete...

Page 4: ...generation The digital test patterns include built in fixed patterns built in pseudorandom patterns and custom user defined test patterns entered via the serial port interface Fabricated in an advanc...

Page 5: ...differential output 733 550 367 733 550 367 733 550 367 mV p p SE2 Input Common Mode 0 9 0 9 0 9 V Input Resistance RFB 250 50 50 50 RFB 500 100 100 100 RFB 15 15 15 k Input Capacitance LI x 22 22 22...

Page 6: ...30 30 30 dB Output Offset 35 35 35 35 35 35 LSB Signal to Noise Ratio SNR fIN 5 MHz at 10 dBFS GAIN 0 V 65 5 64 63 5 dBFS fIN 5 MHz at 1 dBFS GAIN 1 6 V 58 5 57 56 5 dBFS Harmonic Distortion Second Ha...

Page 7: ...ctance Differential LNA gain 15 6 dB 17 9 dB 21 3 dB 5 4 7 3 10 9 5 4 7 3 10 9 5 4 7 3 10 9 mA V Output Level Range Differential CW Doppler output pins 1 5 3 6 1 5 3 6 1 5 3 6 V Input Referred Noise V...

Page 8: ...er Down Dissipation 5 5 5 mW Standby Power Dissipation 148 158 170 mW Power Supply Rejection Ratio PSRR 1 6 1 6 1 6 mV V ADC RESOLUTION 12 12 12 Bits ADC REFERENCE Output Voltage Error VREF 1 V 20 20...

Page 9: ...OGIC INPUT SDIO Logic 1 Voltage Full 1 2 DRVDD 0 3 V Logic 0 Voltage Full 0 0 3 V Input Resistance 25 C 30 k Input Capacitance 25 C 2 pF LOGIC OUTPUT SDIO 3 Logic 1 Voltage IOH 800 A Full 1 79 V Logic...

Page 10: ...ation Delay tCPD 4 Full tFCO tSAMPLE 24 ns DCO to Data Delay tDATA 4 Full tSAMPLE 24 300 tSAMPLE 24 tSAMPLE 24 300 ps DCO to FCO Delay tFRAME 4 Full tSAMPLE 24 300 tSAMPLE 24 tSAMPLE 24 300 ps Data to...

Page 11: ...D2 N 8 D1 N 8 D0 N 8 D10 N 7 MSB N 7 N 1 N tDATA tFRAME tFCO tPD tCPD tEH tEL 07030 002 Figure 2 12 Bit Data Serial Stream Default DCO DCO DOUTx DOUTx FCO FCO AIN CLK CLK D0 LSB D1 N 8 D2 N 8 D3 N 8 D...

Page 12: ...ND 0 3 V to 0 3 V AVDD2 AVDD1 2 0 V to 3 9 V AVDD2 DRVDD 2 0 V to 3 9 V AVDD1 DRVDD 2 0 V to 2 0 V Digital Outputs DOUTx DOUTx DCO DCO FCO FCO GND 0 3 V to 2 0 V CLK CLK GAIN GAIN GND 0 3 V to 3 9 V L...

Page 13: ...97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVDD1 74 75 PDWN 73 STBY 72 DRVDD 71 DOUTA 70 DOUTA 69 DOUTB 68 DOUTB 67 DOUTC 66 DOUTC 65 DOUTD 64 DOUTD 63 FCO 62 FCO 61 DCO 60 DCO...

Page 14: ...Output for Channel G 13 A3 LI G LNA Analog Input for Channel G 14 B3 LG G LNA Ground for Channel G 17 C4 LO H LNA Analog Inverted Output for Channel H 18 D4 LOSW H LNA Analog Switched Output for Chann...

Page 15: ...D 77 C12 LO D LNA Analog Inverted Output for Channel D 78 K10 CWD0 CW Doppler Output Complement for Channel 0 79 J10 CWD0 CW Doppler Output True for Channel 0 80 K9 CWD1 CW Doppler Output Complement f...

Page 16: ...Histogram GAIN 0 16 V 0 2 4 6 10 8 12 14 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 PERCENTAGE OF UNITS GAIN ERROR dB 07030 185 Figure 8 Gain Error Histogram GAI...

Page 17: ...15 6dB LNA GAIN 17 9dB 07030 187 Figure 14 Short Circuit Input Referred Noise vs Frequency PGA Gain 30 dB GAIN 1 6 V 128 129 130 131 132 133 134 135 136 137 138 139 0 0 2 0 4 0 6 0 8 GAIN V 1 0 1 2 1...

Page 18: ...ENCY MHz GAIN 1 6V GAIN 1 0V GAIN 0 5V 07030 123 Figure 20 Third Order Harmonic Distortion vs Input Frequency AIN 1 0 dBFS 120 100 80 60 40 20 0 40 35 30 25 20 15 10 5 0 SECOND ORDER HARMONIC DISTORTI...

Page 19: ...48 120 100 80 60 40 20 0 40 35 30 25 20 15 10 5 0 IMD3 dBFS FUND1 LEVEL dBFS GAIN 1 6V GAIN 0 8V GAIN 0V fIN1 5 00MHz fIN2 5 01MHz FUND2 LEVEL FUND1 LEVEL 20dB 07030 127 Figure 24 IMD3 vs Fundamental...

Page 20: ...e 26 Equivalent LNA Output Circuit 10 10k 10k CLK 10 1 25V CLK 07030 007 Figure 27 Equivalent Clock Input Circuit SDIO 350 30k AVDDx 07030 008 Figure 28 Equivalent SDIO Input Circuit DRVDD DRGND DOUTx...

Page 21: ...7030 012 Figure 32 Equivalent CSB Input Circuit VREF 6k 07030 014 Figure 33 Equivalent VREF Circuit 07030 276 GAIN 50 AVDD2 Figure 34 Equivalent GAIN Input Circuit 07030 176 GAIN 50 70k AVDD2 0 8V Fig...

Page 22: ...gital format immediately following the TGC amplifier and then beam forming is accomplished digitally The ADC resolution of 12 bits with up to 50 MSPS sampling satisfies the requirements of both genera...

Page 23: ...LG x LO x LOSW x VCM VCM VO VO RFB1 RFB2 T R SWITCH TRANSDUCER 07030 101 Figure 39 Simplified LNA Schematic The LNA supports differential output voltages as high as 4 4 V p p with positive and negativ...

Page 24: ...ore significantly At higher frequencies the input capacitance of the LNA needs to be considered The user must determine the level of matching accuracy and adjust RFB accordingly The bandwidth BW of th...

Page 25: ...pedance matching is to improve the transient response of the system With resistive termination the input noise increases due to the thermal noise of the matching resistor and the increased contributio...

Page 26: ...he VGA Immediately following a transmit pulse the typical VGA gains are low and the LNA is subject to overload from T R switch leakage With increasing gain the VGA can become overloaded due to strong...

Page 27: ...H 600 H 700 700 700 700 600 H 600 H 600 H 07030 096 Figure 45 Typical Connection Interface with the AD8333 or AD8339 using the CWDx Outputs LNA AD9273 1nF 500 LO A LOSW A 5k 5k AD8339 2 5V 1nF 500 LNA...

Page 28: ...GAIN LNA ADC 70dB VGA GAIN RANGE 42dB MAX CHANNEL GAIN 48dB 91dB 07030 097 Figure 47 Gain Requirements of TGC Operation for a 12 Bit 40 MSPS ADC The maximum gain required is determined by ADC Noise Fl...

Page 29: ...degraded If the VGA is set for the maximum gain voltage the TGC path is dominated by LNA noise and achieves the lowest input referred noise but with degraded output SNR The higher the TGC LNA VGC gain...

Page 30: ...trolled by the gain interface deter mines the input tap point With overlapping bias currents signals from successive taps merge to provide a smooth attenuation range from 42 dB to 0 dB This circuit te...

Page 31: ...rnal RC filter can be used to remove VGAIN source noise The filter bandwidth should be sufficient to accommodate the desired control bandwidth Antialiasing Filter The filter that the signal reaches pr...

Page 32: ...0 CLK CLK 50 RESISTOR IS OPTIONAL CLK CLK ADC AD9273 PECL DRIVER 3 3V OUT VFAC3 07030 051 AD951x AD952x FAMILY Figure 56 Differential PECL Sample Clock 100 0 1 F 0 1 F 0 1 F 0 1 F AD951x AD952x FAMILY...

Page 33: ...Note for more in depth information about how jitter performance relates to ADCs visit www analog com 1 10 100 1000 16 BITS 14 BITS 12 BITS 30 40 50 60 70 80 90 100 110 120 130 0 125ps 0 5ps 1 0ps 2 0...

Page 34: ...1596 3 standard by using the SDIO pin or via the SPI This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW See the SDIO Pin section or Table 17 for m...

Page 35: ...Figure 65 Data Eye for LVDS Outputs in ANSI 644 Mode with Trace Lengths of Less than 24 Inches on Standard FR 4 400 300 300 200 200 100 100 400 0 1 5ns 0 5ns 1 0ns 0ns 0 5ns 1 0ns 1 5ns EYE DIAGRAM VO...

Page 36: ...the AD9273 DCO is used to clock the output data and is equal to six times the sampling clock rate Data is clocked out of the AD9273 and must be captured on the rising and falling edges of the DCO tha...

Page 37: ...1s and the AD9273 inverts the bit stream with relation to the ITU standard see Table 13 for the initial values Table 13 PN Sequence Sequence Initial Value First Three Output Samples MSB First PN Seque...

Page 38: ...dations It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD9273 An exposed cont...

Page 39: ...nues to process data either reading or writing until CSB is taken high to end the communication cycle This allows complete memory transfers without having to provide additional instructtions Regardles...

Page 40: ...SB tS tDH tHI tCLK tLO tDS tH R W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 07030 068 Figure 70 Serial Timing Details Table 16 Serial Timing Definitions Parameter Minimum Timing ns Description tDS...

Page 41: ...ster 0xFF the duty cycle stabilizer turns off It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers Caution All registers except Register 0x00...

Page 42: ...efault Data Channel D 1 on default 0 off Data Channel C 1 on default 0 off Data Channel B 1 on default 0 off Data Channel A 1 on default 0 off 0x0F Bits are set to determine which on chip device recei...

Page 43: ...ar X X X Output invert 1 on 0 off default 00 offset binary default 01 twos complement 0x00 Configures the outputs and the format of the data Bits 7 3 and Bits 1 0 are global Bit 2 is local 15 OUTPUT_A...

Page 44: ...Enable automatic low pass tuning 1 on self clearing X X High pass filter cutoff 0000 fLP 20 7 0001 fLP 11 5 0010 fLP 7 9 0011 fLP 6 0 0100 fLP 4 9 0101 fLP 4 1 0110 fLP 3 5 0111 fLP 3 1 0x00 Filter cu...

Page 45: ...N OF THE EXPOSED PAD REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET Figure 71 100 Lead Thin Quad Flat Package Exposed Pad TQFP_EP SV 100 3 Dimensions shown in mill...

Page 46: ...Quad Flat Package Exposed Pad TQFP_EP Tape and Reel SV 100 3 AD9273BSVZ 251 40 C to 85 C 100 Lead Thin Quad Flat Package Exposed Pad TQFP_EP SV 100 3 AD9273BSVZRL 251 40 C to 85 C 100 Lead Thin Quad F...

Page 47: ...AD9273 Rev B Page 46 of 48 NOTES...

Page 48: ...AD9273 Rev B Page 47 of 48 NOTES...

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