Analog Devices AD5758, User Manual

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EVAL-AD5758 User Guide UG-1268
Rev. 0 | Page 3 of 20
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5758SDZ evaluation board requires a number of
power supply inputs for AV
DD1
, AV
DD2
, AV
SS
, and V
LOGIC
. AV
DD2
can be connected to AV
DD1
via the AVDD1-AVDD2-SHRT link
if there is only one positive rail available. The V
LOGIC
supply can
be selected from 3.3V_SDP, V
LDO
, or EXT-VLOGIC through the
VLOGIC_SOURCE link. See Table 1 for more link options. See
Table 3 for the default link positions.
The EVAL-AD5758SDZ evaluation board operates with a power
supply range from −33 V on AV
SS
to +33 V on AV
DD1
, with a
maximum voltage between the two rails of 60 V. AV
DD2
requires
a voltage between 5 V and 33 V. V
DPC+
can be driven by AV
DD1
via Jumper JP6. Jumper JP6 bypasses the dc-to-dc circuitry.
SERIAL COMMUNICATION
The EVAL-SDP-CS1Z (SDP-S) system demonstration platform
handles communication to the EVAL-AD5758SDZ via the PC.
By default, the
SDP-S handles the serial port interface (SPI)
communication, controls the RESET and LDAC pins, and
monitors the FAULT pin of the
AD5758 .
The EVAL-AD5758SDZ evaluation board has the option to
disconnect from the
SDP-S and drive the digital signals from an
external source by removing the appropriate links on P2. An
option to tie RESET and LDAC to high or low levels can be
accessed through the S1 and JP11 links.
AD5758 DEVICE UNDER TEST (DUT) ADDRESS PINS
The DUT address pins, AD0 and AD1, are used in conjunction
with the DUT address bits within the SPI frame to determine
which
AD5758 device is being addressed by the system controller.
AD0 and AD1 can be configured through JP12 and JP14.
Table 1. EVAL-AD5758SDZ Link Option Functions
Link Function
AVDD1-AVDD2-SHRT Connects AV
DD2
to AV
DD1
.
VLOGIC_SOURCE Position A selects 3.3 V from the SDP-S . Position B selects 3.3 V from the V
LDO
pin of the AD5758 . Position C selects
the external logic supply, EXT-VLOGIC.
JP1 Position A powers ADR-REF from EXT_REF_VIN. Position B powers ADR-REF from AV
DD2
(the maximum supply for
the ADR4525 is 15 V).
JP2 Selects ADR-REF as the input to REFIN.
JP3 Selects EXT-REF as the input to REFIN.
JP4 Selects REFOUT as the input to REFIN.
JP6 Shorts V
DPC+
to AV
DD1
, bypassing the positive dc-to-dc circuitry.
JP8 Connects VI
OUT
to + V
SENSE
.
JP9 Connects the RETURN signal to GND.
JP10 Connects –V
SENSE
to the RETURN signal.
JP11 Position A connects LDAC to GND. Position B connects LDAC to V
LOGIC
.
JP12 Position A connects AD0 to GND. Position B connects AD0 to V
LOGIC
.
JP14 Position A connects AD1 to GND. Position B connects AD1 to V
LOGIC
.
JP17 Connects AV
SS
to GND for the unipolar supply option (current output only).
P2 Provides options to disconnect from the SDP-S and to drive digital signals from an external source. See Table 2 for
the specific link options.
S1 Position 2-1 (on position to the right of off ) connects RESET to GND. Position 2-3 (on position to the left of off )
connects RESET to V
LOGIC
.