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EVALUATION KITS

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AD5100 Evaluation Board

DOCUMENTATION

Data Sheet

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AD5100: System-Management IC with Programmable
Quad Voltage Monitoring and Supervisory Functions Data
Sheet

REFERENCE MATERIALS

Product Selection Guide

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Supervisory Devices Complementary Parts Guide for
Altera FPGAs

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Supervisory Devices Complementary Parts Guide for
Xilinx FPGAs

DESIGN RESOURCES

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AD5100 Material Declaration

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PCN-PDN Information

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Quality And Reliability

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Symbols and Footprints

DISCUSSIONS

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Summary of Contents for AD5100

Page 1: ...age input antimigration shielding pinouts APPLICATIONS Automotive systems Network equipment Computers controllers and embedded systems GENERAL DESCRIPTION The AD5100 is a factory programmed system management IC that combines four channels of voltage monitoring and watchdog supervision The AD5100 can be used to shut down external supplies reset processors or disable any other system electronics whe...

Page 2: ... Xilinx FPGAs DESIGN RESOURCES AD5100 Material Declaration PCN PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all AD5100 EngineerZone Discussions SAMPLE AND BUY Visit the product page to see pricing options TECHNICAL SUPPORT Submit a technical question or find your regional support number DOCUMENT FEEDBACK Submit feedback for this data sheet This page is dynamicall...

Page 3: ...Supply Monitoring 29 Battery Monitoring with Fan Control 32 Battery State of Charge Indicator and Shutdown Early Warning Monitoring 32 Rising Edge Triggered Wake Up Mode 33 Outline Dimensions 35 Ordering Guide 35 Automotive Products 35 REVISION HISTORY 6 10 Rev 0 to Rev A Changed Programmable to Factory Programmed Throughout 1 Changes to Features Section and General Description Section 1 Changes t...

Page 4: ...SHUTDOWN CONTROLLER RESET GENERATOR WDI DETECTION AND RESET GENERATOR I2C CONTROLLER OTP FUSE ARRAY REGISTER MAP FD REGISTER FAULT DETECTION V1MON 6V TO 30V V4OUT RESET SHDNWARN SHDN MR AD0 SDA SCL VOTP WDI V4MON 0 9V TO 30V V3MON 2 5V TO 5V V2MON 3V TO 30V OV UV AD5100 ON OFF Figure 1 ...

Page 5: ...ltage V2MON Minimum voltage on V2MON to ensure AD5100 VREG power up 2 2 V Voltage Range2 V2MON 3 30 V Input Resistance RIN_V2MON 500 675 860 kΩ On Off Threshold Tolerance3 See Figure 7 and Table 6 ΔOn ΔOff TA 25 C 2 2 TA 40 C to 85 C 2 4 2 4 TA 40 C to 125 C 2 5 2 5 Hysteresis 1 5 Turn On Programmable SHDN Hold Time Tolerance See and Figure 7 Table 8 Δt2SD_HOLD TA 25 C does not apply to Code 0x7 1...

Page 6: ...RCE 30 μA 0 8 V3MON V 2 3 V V3MON 2 7 V ISOURCE 20 μA 0 8 V3MON V 1 8 V V3MON 2 3 V ISOURCE 8 μA 0 8 V3MON V RESET Output Voltage Low VOL V3MON 4 38 V ISINK 3 2 mA 0 4 V V3MON 4 38 V ISINK 1 2 mA 0 3 V RESET Output Short Circuit Current5 ISOURCE RESET 0 V3MON 5 5 V 825 μA RESET 0 V3MON 3 6 V 400 μA Glitch Immune Time tGLITCH 50 μs V4OUT Maximum Output V4OUT_MAX Open drain 5 5 V V4OUT Propagation D...

Page 7: ...2MON IL 0 4 V Device Power Up V2MON Minimum Pulse Width tV2MON_PW 4 ms Device Power Down Delay TVREG_OFF_DELAY V2MON 0 4 V normal mode 2 sec I2 C initiated power down 10 μs 1 Represent typical values at 25 C V1MON 12 V and V2MON 12 V 2 Initial V2MON turn on minimum remains as 2 2 V but the 3 V to 30 V specifications apply afterward 3 Does not apply if V2MON is a digital signal 4 V4MON threshold li...

Page 8: ...3 tLOW low period of SCL clock 1 3 μs t4 tHIGH high period of SCL clock 0 6 50 μs t5 tSU STA setup time for start condition 0 6 μs t6 tHD DAT data hold time 0 9 μs t7 tSU DAT data setup time 0 1 μs t8 tF fall time of both SDA and SCL signals 0 3 μs t9 tR rise time of both SDA and SCL signals 0 3 μs t10 tSU STO setup time for stop condition 0 6 μs 1 Guaranteed by design and not subject to productio...

Page 9: ...perature 260 C 0 C Time at Peak Temperature 20 sec to 40 sec Ramp Up Rate 3 C sec max Ramp Down Rate 6 C sec max Time from 25 C to Peak Temperature 8 minutes max 1 Values relate to the package being used on a 4 layer board 2 TA ambient temperature 3 Junction to case resistance is applicable to components featuring a preferential flow direction for example components mounted on a heat sink Junction...

Page 10: ... logic driver without the pull up resistor ensure that the VIH minimum is 3 3 V 8 SDA I2 C Serial Data Input Output Open drain input output If it is driven directly from a logic driver without the pull up resistor ensure that the VIH minimum is 3 3 V 9 RESET Reset Push pull output with rail voltage of V3MON 10 V4OUT Open Drain Output Triggered by V4MON 11 SHDNWARN Shutdown Warning Active low open ...

Page 11: ...N_OFF is ignored if V2MON_ON but V2MON_OFF cannot be V2MON_ON 3 AD5100 0 default settings Contact Analog Devices if other default settings are required Table 7 Look Up Table of Programming Code vs Typical Thresholds Shown in Table 6 Code V1MON OV Threshold V1MON UV Threshold V2MON On Threshold V2MON Off Threshold V3MON Threshold V4MON Threshold 0000 18 00 V1 8 43 V1 7 47 V1 6 95 V1 2 93 V1 7 54 V1...

Page 12: ...0 0 default settings Contact Analog Devices if other default settings are required Table 9 Look Up Table of Programming Code vs Typical Timings Shown in Table 8 Code t1SD_HOLD t1SD_DELAY t2SD_HOLD t2SD_DELAY tRS_HOLD tWD 000 200 ms1 1200 ms1 10 ms1 100 ms1 200 ms1 1500 ms1 001 150 ms 1000 ms 20 ms 50 ms 150 ms 2000 ms 010 100 ms 800 ms 30 ms 200 ms 100 ms 1250 ms 011 80 ms 400 ms 40 ms 400 ms 50 m...

Page 13: ...10 05692 005 YES NO SHDN 0 SHDN 0 RESET 0 RESET 0 RESET 0 RESET 0 RESET 0 YES NO SHDN 0 V1MON UV V1MON OV YES YES NO SHDN 0 NO SHDN 0 SHDN 1 V2MON ON V2MON OFF V2MON RISING EDGE SENSITIVE SELECTED V2MON LEVEL SENSITIVE SELECTED YES NO CONTINUE MONITORING NO YES V4MON THRESHOLD V4OUT 0 V4OUT 1 NO YES USING V4OUT FOR PWM NO YES V4MON THRESHOLD NO YES V3MON THRESHOLD YES NO VALID WDI YES NO VALID WDI...

Page 14: ...1SD_DELAY The shutdown hold time means that the SHDN signal is held low for t1SD_HOLD after V1MON returns within its UV and OV thresholds The shutdown delay means that the SHDN signal activation is delayed until the programmed t1SD_DELAY has elapsed SHDN activates once the voltage on V1MON is outside the OV or UV threshold for a time longer than tGLITCH RESET follows SHDN delay and hold timings wh...

Page 15: ... programmed threshold by 1 5 before the comparator becomes inactive indicating that the on condition has gone away see Figure 8 When the V2MON input drops below the programmed threshold the comparator becomes active immediately indicating that a V2MON off condition has occurred Similarly due to hysteresis the V2MON input must be brought above the programmed threshold by 1 5 before the comparator b...

Page 16: ...e programmed UV threshold the comparator becomes active immediately indi cating that a UV condition has occurred Due to hysteresis the V3MON input must be brought above the programmed UV threshold by 1 5 before the comparator becomes inactive indicating that the UV condition has gone away see Figure 9 05692 010 V3MON V3MON_UV UV COMPARATOR INACTIVE UV COMPARATOR INACTIVE HYSTERESIS Figure 9 V3MON ...

Page 17: ...s is shown in and the programming code for the selected threshold is found in The default monitoring threshold is 7 54 V Similarly the range of reset hold time is shown in and the programming code of the selected timing is found in Figure 12 Table 6 Table 8 Table 8 Table 9 V4MON exhibits typical input resistance of 675 kΩ that users should take into account for loading effect WATCHDOG INPUT The wa...

Page 18: ...se is generated as per standard mode However if the WDI input remains inactive after three such RESET pulses concurrent with the fourth RESET pulse SHDN is also asserted SHDN is released after 1 second These actions repeat indefinitely unless action is taken by the user if the processor is not responding The advanced WDI and RESET timing diagrams are shown in Figure 14 05692 013 tWDI tWD tWDR tWD ...

Page 19: ...the floating WDI feature can be changed dynamically using the OTP overridden function is selected MANUAL RESET INPUT Manual reset MR is an active low input to the AD5100 and has an internal pull up resistor to V3MON If the input signal on the MR pin goes low RESET is activated MR can be driven from a CMOS logic signal The MR and RESET timing diagrams are shown in Note that Figure 15 RESET is activ...

Page 20: ...r than M2a so SHDN is pulled to the rail which takes AD5100 out of the shutdown mode In some applications the AD5100 may monitor and control power regulators where the input and enable pins are next to each other in a fine pitch This may pose reliability concerns under some abnormal conditions To prevent errors from happen ing the AD5100 shutdown output features smart load detection to ensure that...

Page 21: ...falls below the threshold SHDNWARN outputs a Logic 0 If the processor sees a logic low on this pin the processor may issue an I2 C read command to identify the cause of failure reported in the fault detect status register at Address 0x19 The processor may store the information in external EEPROM as a record of failure history V4OUT OUTPUT V4OUT is an open drain output triggered by V4MON with a min...

Page 22: ... off when V2MON returns to a logic low To configure the part into rising edge triggered mode set the V2MON off threshold register Register 0x04 3 1 to 1001 In this mode once the part is powered on it can only be powered down by an I2 C power down instruction or by removing the supply on the V1MON pin To power down the part over the I2 C bus while in rising edge triggered mode the user must first e...

Page 23: ...nd a resulting long duration high voltage surge is introduced into the supply line Therefore external load dump protection is recommended Typically the load dump overvoltage lasts for a few hundred milliseconds and peaks at around 40 V to 70 V while current can be as high as 1 A As a result a load dump rated TVS D1 and D2 such as SMCJ17 are used to handle the surge energy A series resistor is an i...

Page 24: ...efaults Register writing reading OTP and override are explained in the I2 C Serial Interface section Table 11 AD5100 Register Map Register Address Read Write Permanently Settable Register Name and Bit Description NonOTP Power On Default1 0x01 R W Yes V1MON overvoltage threshold 0x00 18 00 V Bit No Description 3 0 Four bits used to program V1MON OV threshold 7 4 Reserved 0x02 R W Yes V1MON undervol...

Page 25: ...1500 ms Bit No Description 2 0 Three bits used to program watchdog timeout time 7 3 Reserved 0x0D R W Yes RESET configuration 0x00 Bit No Description 0 0 RESET is active when SHDN is active 1 RESET is not active when SHDN is active 1 0 RESET active low 1 RESET active high 2 0 enables V4MON under threshold causing RESET 1 prevents V4MON under threshold from causing RESET for V4OUT applications 3 0 ...

Page 26: ...ertion of SHDN pin 7 5 Reserved 0x19 Read only No Fault detect and status Bits 3 0 are level triggered bits that indicate the current state of the comparators monitoring the V1MON and V2MON input pins Bits 6 4 are edge triggered fault detection bits that indicate what error conditions were present when a SHDN event occurred 0x40 Bit No Description 0 1 V2MON input V2MON off threshold 1 1 V2MON inpu...

Page 27: ...ointer sets up one of the other registers for the second byte of the write operation or for a subsequent read operation Table 12 shows the structure of the address pointer register Bits 6 0 signify the address of the register that is to be written to or read from Bit 7 is a reserved bit and should be 0 for normal write read operations Table 12 Address Pointer Register Structure Bit Number Function...

Page 28: ...n Figure 23 If the address pointer is known to be already at the desired address data can be read from the corresponding data register without first writing to the address pointer register Table 14 shows the readback data byte structure Bits 6 0 con tain the data from the register just read Bit 7 is a reserved bit and should be ignored for normal read operations The majority of AD5100 registers ar...

Page 29: ...erridden register to its default setting the following sequence should be used 1 Set Bit 3 0 in Register 0x16 2 Write a dummy byte to the register of choice Clearing the override bit in Register 0x16 does not cause all overridden registers to revert to their defaults at the same time For example imagine that the user overrides Register 0x01 Register 0x02 and Register 0x03 If the user subsequently ...

Page 30: ...tor the signals from a car battery and an ignition key in an automobile respectively see Figure 24 The shutdown output can be connected to the shutdown pin of an external regulator to prevent false condi tions such as a weak battery or overcharging of a battery by an alternator The reset output can be used to reset the processor in the event of a hardware or software malfunction An example of the ...

Page 31: ...D AND DELAY RESET GENERATOR AND ADJUSTABLE RESET HOLD DRIVER PROGRAMMABLE DRIVER LOAD DESELECT 1 3 2 RESET GENERATOR PROGRAMMABLE WATCHDOG OTP FUSE ARRAY MEMORY MAP FD REGISTER FAULT DETECTION 4 TIMES I 2 C CONTROLLER SET CONFIGURATIONS PROGRAM PARAMETERS READ STATUS I 2 C SHDN SHDNWARN V 4OUT RESET PA VCC DAC VOUT GND VIN VOUT V REG2 SD GND VIN 3 3 5V V REG1 SD VDD DVDD 1 8V 3 3V I O I O DSP MICR...

Page 32: ...NOUT RESET WDI RESET WDI RESET V2MON OFF SHUTDOWN SHUTDOWN ENABLE RESET MR RESET SHDN MR RESET tVREG_OFF_DELAY tVREG_ON_DELAY MICROPROCESSOR FAILED RESET HIGH Z UV SHUTDOWN SHUTDOWN ENABLE RESET MICROPROCESSOR FAILED SHUTDOWN Figure 25 Example of SHDN and RESET Responses of Circuit Shown in Figure 24 ...

Page 33: ...If the battery remains at the low voltage level it is indeed a poor battery However there is no way to warn the driver As a result the system designer can use V4OUT as the battery warning indicator By stepping down the battery voltage monitored at V4MON the LED is lit which gives a battery replacement warning The circuit is shown in Figure 28 05692 027 AD5100 V2MON V3MON V4MON MR WDI SDA SCL V1MON...

Page 34: ...e external regulator is turned on to supply power to the microprocessor A reset pulse train is generated at the reset output if there is no watchdog activity The pulse continues until the correct watchdog signal appears at the AD5100 WDI pin The shutdown pin remains high as long as the AD5100 continues to receive the correct watchdog signal When the microprocessor finishes its housekeeping tasks o...

Page 35: ...ULSE S VREG VI VO SD MICROPROCESSOR VDD I O RS I O I O Figure 29 Rising Edge Triggered Wake Up Mode 05692 031 SCL NOTES 1 6V V1MON 30V 2 SELECT V2MON_OFF RISING EDGE TRIGGER CAN WAKE UP MODE SDA WRITE V2MON WDI SCL SDA RESET SHDN Figure 30 Rising Edge Triggered Operation of Circuit Shown in Figure 29 ...

Page 36: ...tion Package Option Ordering Quantity AD5100YRQZ 0 40 C to 125 C 16 Lead QSOP RQ 16 AD5100YRQZ 1RL7 40 C to 125 C 16 Lead QSOP RQ 16 1 000 AD5100YRQZ 1REEL 40 C to 125 C 16 Lead QSOP RQ 16 2 500 EVAL AD5100EBZ Evaluation Board 1 Z RoHS Compliant Part 2 AD5100YRQZ 0 Non OTP programmed part intended for evaluation purposes only AUTOMOTIVE PRODUCTS The AD5100 models are available with controlled manu...

Page 37: ... to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors 2009 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05692 0 6 10 A ...

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