AMIMON AMN11310 WHDI, Datasheet

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Interfaces
Version 0.4
AMIMON Confidential 13
3.3.1.3 MAC uC Write Operation
Figure 8 demonstrates a write transaction which sends 2 data bytes and which ends with the master stop bit.
Each write transaction sends 1 or more data bytes to the MAC, beginning at an explicit 2 bytes long address.
Multiple data bytes may be written as the MAC stores the received register data until the master sends a stop bit.
The MAC updates the register value upon a successful termination of a write transaction.
I
6
write I
5
...
Two-Wire Slave address ack
A
15
A
8
A
14
...
register address ack
A
7
A
0
A
6
...
register address ack
D7 D0 D6
...
register data0 ack
D
7
D
0
D
6
...
register data1 ack
STOP START
Figure 8: Two-Wire MAC Write Commands
3.3.1.4 MAC uC Read Operation
This operation reads from a specific 2-byte address. The read transaction is divided into two parts. In the first
part, the Two-Wire master sends a write command to the slave containing only the required start address. (The
address is always 2 bytes long.) In the second part, multiple bytes may be read from consecutive addresses. The
MAC puts the appropriate data on the Two-Wire bus and the internal address is automatically incremented. A
stop bit is sent by the master only when the entire transaction has been completed.
I
6
write I
5
...
Two-Wire Slave address ack register address ack register address
START
ack
A
15
A
8
A
14
...
A
7
A
0
A
6
...
I
6
read I
5
...
Two-Wire slave address ack
START Data Byte 0
register data ack
Data Byte 1
register data ack
STOP
Figure 9: Two-Wire Read Command
3.3.1.5 WHDI Application/MAC Protocol
The WHDI programmer’s reference defines the MAC registers data structure. Each register has an associated
group ID and index offset address.
The group ID and the index offset are each 1 byte long. Together they define a register address that is 2 bytes
long.
Each register has an attributed length (in byte units). All registers within the same group have the same length.
A Two-Wire transaction to a specific register includes 2 bytes of register address and the register data bytes. The
register is written in one transaction. If the transaction terminates ahead of time or is too long, the MAC issues an
error interrupt and does not store the received values. The register is read in one transaction, as described in
section
3.3.1.4. If the read transaction finishes ahead of time, the MAC issues an error interrupt.
3.3.2 Interrupts
There is one interrupt connected to the WHDI connector. The interrupt source is the AMN2110 MAC uC. For
details about the interrupt, please refer to the
Programmer's User Guide . The interrupt active polarity is set in SW
or by configuration resistors on board – see 3.3.3.