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Set the Event Status Enable register, which is a 8-bit register, i.e. a
value between 0 and 255 must be specified as argument
6.3.3
*ESE?
SCPI standard command (standard Event Status Enable query).
Outputs the value of the Event Status Enable register.
6.3.4
*ESR?
SCPI standard command (standard Event Status Register query).
Outputs the value of the Event Status Register.
This implementation supports the following bits in the ESR register (if
enabled with the ESE register):
•
Power ON (PON, bit 7): This bit is set to 1 after power up.
•
Command Error (CME, bit 5): This bit is set when an unknown
command has been received or a known command with
wrong arguments has been received.
•
EXE (bit 4): This bit is set when an error during the execution
of a command has occurred.
•
Operation Complete (OPC, bit 0): Is set whenever a command
has been executed.
The events in the ESR register are cleared after a read.
6.3.5
*IDN?
SCPI standard command (Identification query). Return information for
the unit in the format <manufacture>,<model>,<serial#>,<version>,
e.g.:
AMETEK,ASM801A,123456-12345, 1.00
6.3.6
*OPC
SCPI standard command (Operation Complete).
Because the system only implements sequential commands this
command will immediately set the OPC bit in the Event Status
Register when the command is executed.
