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44409
Rev.
1.70
October 10
AMD SP5100 Databook
Signal Description
43
7.15 General Purpose I/O
The GPIO pins of the SP5100 are multiplexed with other functions. For information on how to configure
the GPIO pins for the desired functions, see the
AMD SP5100 Register Reference Guide.
The table below lists all the GPIO pins on the SP5100. The Default Type column shows the state of the
pin (default function) after de-assertion of the PCI host bus reset (A_RST#), which happens after power
up or after system reset. Signals that are in input state after reset will be tri-state (TS) if they do not have
any internal PU (pull up ) or PD (Pull Down). For pins that have PU or PD internally, their states after
reset will depend on the PU or PD: for signals with PU, the state will be HIGH and for signals with PD the
state will be LOW. The PU and PD shown are enabled by default after PCI Reset and can be disabled by
System BIOS.
Ball Name
(
Default Function
in Blue
)
Type
Voltage and
Domain
Internal
Resistor
(
Default in
Blue
)
Default
Type
(
Default
State in
Blue
)
Functional Description
CLK_REQ0#/
SATA_IS3#/
GPIO0
I/O
3.3V_S0
(5-V Tolerance)
10-k
Ω PU
10-k
Ω PD
Input
Clock Request 0/
Serial ATA Interlock 3/
GPIO 0
SPKR/
GPIO2
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
Speaker/
GPIO 2
FANOUT0/
GPIO3
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
Fan Output 0/
GPIO 3
SMARTVOLT1/
SATA_IS2#/
GPIO4
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
Smartvolt Select 1/
Serial ATA Interlock 2/
GPIO 4
SMARTVOLT2/
SHUTDOWN#/
GPIO5
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
Smartvolt Select 2/ System
Shutdown/
GPIO 5
CLK_REQ3#/
SATA_IS1#/
GPIO6
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
TS
Clock Request 3/
Serial ATA Interlock 1/
GPIO 6
DDC1_SDA/
GPIO8
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
DDC1 Serial Data/
GPIO 8
DDC1_SCL/
GPIO9
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
DDC1 Serial Control/
GPIO 9
SATA_IS0#
/
GPIO10
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Input
Serial ATA Interlock 0/
GPIO 10
SPI_DO
/
GPIO11
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
SPI ROM Data Out/
GPIO 11
SPI_DI
/
GPIO12
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Input
SPI ROM Data In/
GPIO 12
LAN_RST#
/
GPIO13
I/O
3.3V_S0
(5-V Tolerance)
8.2-k
Ω PU
8.2-k
Ω PD
Output
Low
LAN Reset/
GPIO 13
ROM_RST#
/
GPIO14
I/O
3.3V_S5
10-k
Ω PU
10-k
Ω PD
Output
Low
SPI ROM Reset/
GPIO 14
IDE_D[6:0]
/
GPIO[21:15]
I/O
3.3V_S0
(5-V Tolerance)
27-
Ω series
Output
High
IDE data [6:0]/
GPIO [21:15]
IDE_D7
/
GPIO22
I/O
3.3V_S0
(5-V Tolerance)
27-
Ω series
10-k
Ω PD
Output
High
IDE data 7/
GPIO 22