![background image](http://html1.mh-extra.com/html/amd/sp5100/sp5100_data-book_2921669021.webp)
44409
Rev.
1.70
October 10
AMD SP5100 Databook
SP5100 Strap Information
21
S5 3.3V /S5 1.2V
RSM_RST#
System dependent (10
ms or greater)
31 ms
T1
25 ms
2RTC
Strap signal must be
stable and at valid state
Strap signal is tristate can be High
or Low
25 ms
Strap signal is tristate
can be High or Low
RTC_CLK
Figure 4-3: Type I Straps Capture timing
Straps are also classified in two groups, standard and debug. Straps in the standard group are used for
selecting on power up the desired modes of ASIC operation and additional optional features. Straps in
debug group are for debugging at the system-level, mainly during the pre-production stage. Debug straps
should have provision for PU or PD so they can be configured to either option when required for debug
purposes.
show the function of every strap signal in the design. All straps are defined such
that in the most likely scenario of operation, they will be set to the recommended (or safest) values. The
values shown in the Description column are the external board strap values, with 3.3V being a pull-up
(PU) and 0V a pull-down (PD).
Table 4-1: Standard Straps
Pad Name
Strap Name
Type
Description
{IMCGPIO17,
IMCGPIO16 }
{ ROM_TYPE_1,
ROM_TYPE_0 }
I
ROM_TYPE_1
ROM_TYPE_0
ROM Type
3.3 V
3.3 V
Reserved
3.3 V
0 V
SPI ROM
0 V
3.3 V
LPC ROM (Supports
both LPC and PMC
ROM types)
0 V
0 V
Firmware Hub
These two strap pins should be configured to the
corresponding state that matches the Hardware
ROM type installed.