AMD Geode™ SC1200/SC1201 Processor Data Book
185
Core Logic Module - Register Summary
32579B
Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
F5 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 6-39)
00h-01h
16
RO
Vendor Identification Register
100Bh
Page 277
02h-03h
16
RO
Device Identification Register
0505h
Page 277
04h-05h
16
R/W
PCI Command Register
0000h
Page 277
06h-07h
16
RO
PCI Status Register
0280h
Page 277
08h
8
RO
Device Revision ID Register
00h
Page 277
09h-0Bh
24
RO
PCI Class Code Register
068000h
Page 277
0Ch
8
RO
PCI Cache Line Size Register
00h
Page 277
0Dh
8
RO
PCI Latency Timer Register
00h
Page 277
0Eh
8
RO
PCI Header Type Register
00h
Page 277
0Fh
8
RO
PCI BIST Register
00h
Page 277
10h-13h
32
R/W
Base Address Register 0 (F5BAR0) — Sets the base address for
the X-Bus Expansion support registers (summarized in
Table 6-25.)
00000000h
Page 277
14h-17h
32
R/W
Base Address Register 1 (F5BAR1) — Reserved for possible
future use by the Core Logic module.
00000000h
Page 277
18h-1Bh
32
R/W
Base Address Register 2 (F5BAR2) — Reserved for possible
future use by the Core Logic module.
00000000h
Page 277
1Ch-1Fh
32
R/W
Base Address Register 3 (F5BAR3) — Reserved for possible
future use by the Core Logic module.
00000000h
Page 278
20h-23h
32
R/W
Base Address Register 4 (F5BAR4) — Reserved for possible
future use by the Core Logic module.
00000000h
Page 278
24h-27h
32
R/W
Base Address Register 5 (F5BAR5) — Reserved for possible
future use by the Core Logic module.
00000000h
Page 278
28h-2Bh
---
---
Reserved
00h
Page 278
2Ch-2Dh
16
RO
Subsystem Vendor ID
100Bh
Page 278
2Eh-2Fh
16
RO
Subsystem ID
0505h
Page 278
30h-3Fh
---
---
Reserved
00h
Page 278
40h-43h
32
R/W
F5BAR0 Base Address Register Mask
FFFFFFC1h
Page 278
44h-47h
32
R/W
F5BAR1 Base Address Register Mask
00000000h
Page 279
48h-4Bh
32
R/W
F5BAR2 Base Address Register Mask
00000000h
Page 279
4Ch-4Fh
32
R/W
F5BAR3 Base Address Register Mask
00000000h
Page 279
50h-53h
32
R/W
F5BAR4 Base Address Register Mask
00000000h
Page 279
54h-57h
32
R/W
F5BAR5 Base Address Register Mask
00000000h
Page 279
58h
8
R/W
F5BARx Initialized Register
00h
Page 279
59h-FFh
---
---
Reserved
xxh
Page 279
60h-63h
32
R/W
Scratchpad for Chip Number
00000000h
Page 279
64h-67h
32
R/W
Scratchpad for Configuration Block Address
00000000h
Page 280
68h-FFh
---
---
Reserved
Page 280
Table 6-25. F5BAR0: I/O Control Support Registers Summary
I/O Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 6-40)
00h-03h
32
R/W
I/O Control Register 1
010C0007h
Page 281
04h-07h
32
R/W
I/O Control Register 2
00000002h
Page 281
08h-0Bh
32
R/W
I/O Control Register 3
00009000h
Page 282
Summary of Contents for Geode SC1200
Page 8: ...8 AMD Geode SC1200 SC1201 Processor Data Book List of Figures 32579B...
Page 16: ...16 AMD Geode SC1200 SC1201 Processor Data Book Overview 32579B...
Page 24: ...24 AMD Geode SC1200 SC1201 Processor Data Book Architecture Overview 32579B...
Page 364: ...364 AMD Geode SC1200 SC1201 Processor Data Book Debugging and Monitoring 32579B...