AMD Geode SC1200 Data Book Download

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AMD Geode™ SC1200/SC1201 Processor Data Book

AMD Geode™ SC1200/SC1201
Processor Data Book

March 2006

Publication ID: 32579B

Summary of Contents for Geode SC1200

Page 1: ...AMD Geode SC1200 SC1201 Processor Data Book AMD Geode SC1200 SC1201 Processor Data Book March 2006 Publication ID 32579B...

Page 2: ...or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in...

Page 3: ...27 3 2 Strap Options 44 3 3 Multiplexing Configuration 45 3 4 Signal Descriptions 49 4 0 General Configuration Block 71 4 1 Configuration Block Addresses 71 4 2 Pin Multiplexing Interrupt Selection an...

Page 4: ...Functional Description 313 7 3 Register Descriptions 333 8 0 Debugging and Monitoring 363 8 1 Testability JTAG 363 9 0 Electrical Specifications 365 9 1 General Specifications 365 9 2 DC Characteristi...

Page 5: ...tions 121 Figure 5 15 ACCESS bus Data Transaction 122 Figure 5 16 ACCESS bus Acknowledge Cycle 122 Figure 5 17 A Complete ACCESS bus Data Transaction 123 Figure 5 18 UART Mode Register Bank Architectu...

Page 6: ...ming Measurement Conditions 392 Figure 9 18 PCI Input Timing Measurement Conditions 393 Figure 9 19 PCI Reset Timing 393 Figure 9 20 Sub ISA Read Operation Timing Diagram 396 Figure 9 21 Sub ISA Write...

Page 7: ...ing Diagram 429 Figure 9 52 AC97 Rise and Fall Timing Diagram 430 Figure 9 53 AC97 Low Power Mode Timing Diagram 431 Figure 9 54 PWRBTN Trigger and ONCTL Timing Diagram 432 Figure 9 55 GPWIO and ONCTL...

Page 8: ...8 AMD Geode SC1200 SC1201 Processor Data Book List of Figures 32579B...

Page 9: ...ard Configuration Registers 95 Table 5 4 SIO Control and Configuration Register Map 97 Table 5 5 SIO Control and Configuration Registers 97 Table 5 6 Relevant RTC Configuration Registers 98 Table 5 7...

Page 10: ...138 Table 5 56 Bank 1 Bit Map 139 Table 5 57 Bank 2 Bit Map 139 Table 5 58 Bank 3 Bit Map 139 Table 5 59 Bank 4 Bit Map 139 Table 5 60 Bank 5 Bit Map 140 Table 5 61 Bank 6 Bit Map 140 Table 5 62 Bank...

Page 11: ...6 45 Programmable Interval Timer Registers 302 Table 6 46 Programmable Interrupt Controller Registers 304 Table 6 47 Keyboard Controller Registers 307 Table 6 48 Real Time Clock Registers 308 Table 6...

Page 12: ...arameters 417 Table 9 32 UART Sharp IR SIR and Consumer Remote Control Timing Parameters 421 Table 9 33 Fast IR Port Timing Parameters 422 Table 9 34 Standard Parallel Port Timing Parameters 423 Table...

Page 13: ...CI bus interface an LPC bus interface Advanced Configuration Power Inter face ACPI version 1 0 compliant power management and an audio codec interface The SuperI O module has three serial ports UART1...

Page 14: ...ffer compress decompress Hardware cursor 32x32 pixels Video Processor Module Video Accelerator Flexible video scaling support of up to 8x horizon tally and vertically Bilinear interpolation filters wi...

Page 15: ...16 MB addressing Supports a chip select for ROM or Flash EPROM boot device Supports either M Systems DiskOnChip DOC2000 Flash file system NAND EEPROM Supports up to two chip selects for external I O d...

Page 16: ...16 AMD Geode SC1200 SC1201 Processor Data Book Overview 32579B...

Page 17: ...8 1 1 Specifica tion Update documents The SC1200 SC1201 processor s device ID is contained in the GX1 module Software can detect the revision by read ing the DIR0 and DIR1 Configuration registers see...

Page 18: ...22 RSVD Reserved Write as 0 21 RSVD Reserved Must be written as 0 Wait state on the X Bus x_data during read cycles for debug only 20 18 SDCLKRATE SDRAM Clock Ratio Selects SDRAM clock ratio 000 Reser...

Page 19: ...ite as 0 13 12 SDCLKCTL SDCLK High Drive Slew Control Controls the high drive and slew rate of SDCLK 3 0 and SDCLK_OUT 11 is strongest 00 is weakest 11 RSVD Reserved Write as 0 10 SDCLKOMSK Enable SDC...

Page 20: ...f output data This parameter significantly affects system performance Optimal setting should be used If an SODIMM is used BIOS can interrogate EEPROM across the ACCESS bus interface to determine this...

Page 21: ...Test Enable TEST 3 0 0 TEST 3 0 are driven low normal operation 1 TEST 3 0 pins are used to output test information 16 TECTL Test Enable Shared Control Pins 0 RASB CASB CKEB WEB normal operation 1 RAS...

Page 22: ...ovide a summary of how the Video Processor interfaces with the other modules of the SC1200 SC1201 processor For detailed information about the Video Pro cessor see Section 7 0 on page 311 2 2 1 GX1 Mo...

Page 23: ...is cleared SUSP and SUSPA are handshake signals for imple menting CPU Clock Stop and clock throttling CPU_RST resets the CPU and is asserted for approxi mately 100 s after the negation of POR PCI bus...

Page 24: ...24 AMD Geode SC1200 SC1201 Processor Data Book Architecture Overview 32579B...

Page 25: ...T TFTD15 SLIN ASTRB TFTD16 STB WRITE TFTD17 Parallel Port IDE_ADDR2 TFTD4 IDE_DATA15 TFTD7 IDE_IOR0 TFTD10 IDE_IOW0 TFTD9 IDE_CS0 TFTD5 IDE_IORDY0 TFTD11 IDE_DREQ0 TFTD8 IDE_DACK0 TFTD0 IRQ14 TFTD1 ID...

Page 26: ...EL3 AC97_CLK AC97_RST GPIO16 PC_BEEP Power CLK32 GPWIO 2 0 LED ONCTL PWRBTN PWRCNT 1 2 THRM TCK TDI TDO TMS TRST JTAG TEST1 PLL6B TEST0 PLL2B TEST3 GXCLK FP_VDD_ON TEST2 PLL5B GTEST Test and TDP TDN G...

Page 27: ...PIO and LPC Registers Function 0 on page 190 2 Configuration settings listed in this table are with regard to the Pin Multiplexing Register PMR See Section 4 2 Pin Multiplexing Interrupt Selection and...

Page 28: ...GP35 GP34 GP33 VSS AD7 VIO AD8 GP32 GP13 VIO VSS AD3 AD6 AD5 VSS AD4 ICS1 AD1 VCORE VSS GP12 AB1D AB1C VCORE SDO SYNC ACCK VSS VSS VSS VSS VCORE VCORE VCORE VCORE AD0 IAD2 AD2 VCORE IDAT15 IDAT14 IDAT...

Page 29: ...WIRE AVC CCRT A16 VSS GND A17 VPLL2 PWR A186 2 PD7 I O INT O14 14 VIO PMR 23 3 0 and PMR 27 0 and FPCI_MON 0 TFTD13 O O1 4 PMR 23 3 1 and PMR 27 0 and FPCI_MON 0 F_AD7 O O14 14 PMR 23 3 0 and PMR 27...

Page 30: ...PMR 23 3 0 and PMR 27 0 and FPCI_MON 0 TFTDE O O1 4 PMR 23 3 1 and PMR 15 0 and PMR 27 0 and FPCI_MON 0 VOPCK O O1 4 PMR 23 3 1 and PMR 15 1 and PMR 27 0 and FPCI_MON 0 FPCICLK O O1 4 PMR 23 3 0 and P...

Page 31: ...I_MON 0 F_AD4 O O14 14 PMR 23 3 0 and PMR 27 1 or FPCI_MON 1 Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration C196 2 PD5 I O INT O14 14 VIO PMR 23 3 0 and PMR 27 0 and FPCI_MON 0 TF...

Page 32: ...1 and PMR 15 1 and PMR 13 0 IOCS1 O PU22 5 O3 5 VIO PMR 23 3 0 and PMR 13 1 or PMR 23 3 1 and PMR 15 1 and PMR 13 1 TFTD12 O PU22 5 O1 4 VIO PMR 23 3 1 and PMR 15 0 Ball No Signal Name I O PU PD Buffe...

Page 33: ...ed BHE O OPCI E28 SIN2 I INTS VIO PMR 28 0 SDTEST3 O O2 5 PMR 28 1 E29 TRST I PU22 5 INPCI VIO E30 TDO O OPCI VIO E31 TCK I PU22 5 INPCI VIO Ball No Signal Name I O PU PD Buffer1 Type Power Rail Confi...

Page 34: ...exed A9 O OPCI Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration L3 AD10 I O INPCI OPCI VIO Cycle Multiplexed A10 O OPCI L4 AD12 I O INPCI OPCI VIO Cycle Multiplexed A12 O OPCI L28 G...

Page 35: ...O OAC97 VIO TFT_PRSNT I PD100 INSTRP VIO Strap See Table 3 4 on page 44 P30 SYNC O OAC97 VIO CLKSEL3 I PD100 INSTRP Strap See Table 3 4 on page 44 P31 AC97_CLK O O2 5 VIO PMR 25 1 R1 VSS GND R2 VSS G...

Page 36: ...al Name I O PU PD Buffer1 Type Power Rail Configuration W19 VCORE PWR W286 MD57 I O INT TS2 5 VIO W29 SDCLK1 O O2 5 VIO W30 VSS GND W31 VIO PWR Y15 IDE_DATA10 I O INTS1 TS1 4 VIO PMR 24 0 DDC_SCL O OD...

Page 37: ...INTS VIO AF286 MD50 I O INT TS2 5 VIO AF296 MD49 I O INT TS2 5 VIO AF306 MD54 I O INT TS2 5 VIO AF316 MD53 I O INT TS2 5 VIO Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AG1 GP...

Page 38: ...OD14 VSB AK7 VSS GND AK8 IRRX1 I INTS VSB PMR 6 0 SIN3 I INTS VIO PMR 6 1 Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AK96 MD1 I O INT TS2 5 VIO AK10 VSS GND AK116 MD7 I O INT...

Page 39: ...PE SLCT SLIN ASTRB STB WRITE ONCTL PWRCNT 2 1 3 The TFT_PRSNT strap determines the power on reset POR state of PMR 23 4 The LPC_ROM strap determines the power on reset POR state of PMR 14 and PMR 22...

Page 40: ...13 D15 AVCCTV D23 AVCCUSB D27 AVSSCRT B14 C14 C15 AVSSPLL2 C16 AVSSPLL3 AK3 AVSSTV B24 AVSSUSB C27 BA0 AJ13 BA1 AK14 BHE E4 BIT_CLK U30 BLUE A15 BOOT16 C8 BUSY WAIT B17 C BE0 L1 C BE1 J2 C BE2 F3 C BE...

Page 41: ...DATA3 AB4 IDE_DATA4 AB1 IDE_DATA5 AA4 IDE_DATA6 AA3 IDE_DATA7 AA2 IDE_DATA8 Y3 IDE_DATA9 Y2 IDE_DATA10 Y1 IDE_DATA11 W4 IDE_DATA12 W3 IDE_DATA13 V3 IDE_DATA14 V2 IDE_DATA15 V1 IDE_DREQ0 AC4 IDE_DREQ1...

Page 42: ...B5 REQ1 A5 RI2 AJ8 ROMCS C8 RTS2 C30 SDATA_IN U31 SDATA_IN2 AL8 SDATA_OUT P29 SDCLK_IN AJ27 SDCLK_OUT AK28 SDCLK0 AJ21 SDCLK1 W29 SDCLK2 AA28 SDCLK3 V29 SDTEST0 C30 SDTEST1 B29 SDTEST2 C28 SDTEST3 E28...

Page 43: ...0 VPCKIN F31 VPD0 J30 Signal Name Ball No VPD1 J29 VPD2 J28 VPD3 H31 VPD4 H30 VPD5 H29 VPD6 H28 VPD7 G31 VPLL2 A17 VPLL3 AJ4 VREF D16 VSB AL5 VSBL AL6 Signal Name Ball No VSS Total of 91 A1 A13 A16 A1...

Page 44: ...nded Value programmed at reset by CLKSEL 3 0 Note Values for GCB I O Offset 10h 3 0 and 1Eh 3 0 are not the same CLKSEL1 SOUT1 AF3 PD100 CLKSEL2 SOUT2 D29 PD100 CLKSEL3 SYNC P30 PD100 BOOT16 ROMCS C8...

Page 45: ...xed with GPIO except GPIO12 GPIO13 and GPIO16 Table 3 5 Two Signal Group Multiplexing Ball No Default Alternate Signal Configuration Signal Configuration IDE TFT CRT PCI GPIO System AD3 IDE_ADDR0 PMR...

Page 46: ...and PMR 22 1 L31 GPIO33 LAD1 L30 GPIO34 LAD2 L29 GPIO35 LAD3 L28 GPIO36 LDRQ K31 GPIO37 LFRAME K28 GPIO38 IRRX2 LPCPD J31 GPIO39 SERIRQ UART Internal Test E28 SIN2 PMR 28 0 SDTEST3 PMR 28 1 AC97 FPCI...

Page 47: ...R 23 1 and PMR 15 1 and PMR 7 1 TFTD0 PMR 23 1 and PMR 15 0 D10 GPIO1 PMR 23 0 and PMR 13 0 or PMR 23 1 and PMR 15 1 and PMR 13 0 IOCS1 PMR 23 0 and PMR 13 1 or PMR 23 1 and PMR 15 1 and PMR 13 1 TFTD...

Page 48: ...Port TFT VOP FPCI Monitoring B18 ACK PMR 23 0 and PMR 27 0 and FPCI_MON 0 TFTDE PMR 23 1 and PMR 15 0 and PMR 27 0 and FPCI_MON 0 VOPCK PMR 23 1 and PMR 15 1 and PMR 27 0 and FPCI_MON 0 FPCI_CLK PMR 2...

Page 49: ...must be used ROMCS LPC_ROM D6 I LPC ROM This strap signal forces selecting of the LPC bus and sets bit F0BAR1 I O Offset 10h 15 LPC ROM Addressing Enable It enables the SC1200 SC1201 pro cessor to bo...

Page 50: ...It is asserted for approximately 100 s after POR is negated 3 4 1 System Interface Continued Signal Name Ball No Type Description Mux 3 4 2 Memory Interface Signals Signal Name Ball No Type Descriptio...

Page 51: ...se signals should have an external pull down resistor of 33 K SDCLK3 V29 O SDRAM Clocks SDRAM uses these clocks to sample all control address and data lines To ensure that the Suspend mode functions c...

Page 52: ...ay Data Channel interface It is used for monitor communications The DDC2B standard is supported by this interface IDE_DATA10 DDC_SDA Y2 I O DDC Serial Data This is the bidirectional serial data sig na...

Page 53: ...to enable power to the Flat Panel display with power sequence timing IDE_DATA4 V30 GXCLK TEST3 TFTD 17 0 See Table 3 3 on page 40 O Digital RGB Data to TFT TFTD 5 0 Connect to BLUE TFT inputs TFTD 11...

Page 54: ...tensity Color intensity vector Cr C23 D24 O Chrominance Red Red axis phase angle Cb A24 C23 O Chrominance Blue Blue axis phase angle TVREF C24 I O Voltage Reference Reference voltage for TV DAC This s...

Page 55: ...CICLK0 A4 O PCI Clock Outputs PCICLK0 and PCICLK1 provide clock drives for the system at 33 MHz These clocks are asynchronous to PCI signals There is low skew between all outputs One of these clock si...

Page 56: ...uration of an access FRAME is asserted to indicate the beginning of a bus transaction While FRAME is asserted data transfers continue FRAME is de asserted when the transaction is in the final data pha...

Page 57: ...ete When LOCK is asserted non exclusive transactions may pro ceed to an address that is not currently locked at least 16 bytes must be locked A grant to start a transaction on PCI does not guarantee c...

Page 58: ...s enabled in the GX1 module s PCI Control Function 2 register Index 41h 5 SERR is asserted upon asser tion of PERR This signal is internally connected to a pull up resistor REQ1 A5 I Request Lines REQ...

Page 59: ...nal timing is as follows In a read cycle TRDE has the same timing as RD In a write cycle TRDE is asserted to active low at the time WR is asserted It continues being asserted for one PCI clock cycle a...

Page 60: ...request for LPC interface Note If LDRQ function is selected but not used tie LDRQ high GPIO36 LFRAME K31 O LPC Frame A low pulse indicates the beginning of a new LPC cycle or termination of a broken...

Page 61: ...C28 O GPIO9 DCD2 SDTEST2 IDE_CS0 AF2 O IDE Chip Selects 0 and 1 These signals are used to select the command block registers in an IDE device TFTD5 IDE_CS1 P2 O TFTDE IDE_IORDY0 AD1 I I O Ready Channe...

Page 62: ...then signal s should be tied high SIN2 E28 SDTEST3 SIN3 AK8 IRRX1 SOUT1 AF3 O Serial Outputs Send composite serial data to the com munications link peripheral device modem or other data transfer devi...

Page 63: ...s Signal Name Ball No Type Description Mux ACK B18 I Acknowledge Pulsed low by the printer to indicate that it has received data from the Parallel Port TFTDE VOPCK FPCICLK AFD DSTRB D22 O Automatic Fe...

Page 64: ...data cycle When the cycle is aborted ASTRB becomes inactive high TFTD16 F_IRDY STB WRITE A22 O Data Strobe When low indicates to the printer that valid data is available at the printer port This signa...

Page 65: ...transfer of data between the SC1200 SC1201 processor and the AC97 codec CLKSEL3 Strap AC97_CLK P31 O Codec Clock It is twice the frequency of the Audio Bit Clock AC97_RST U29 O Codec Reset S3 to S5 wa...

Page 66: ...above avoided the power button must be toggled This can be done externally or internally GPIO63 is internally connected to PWRBTN To toggle the power button with software GPIO63 must be programmed as...

Page 67: ...GPIO7 C30 RTS2 IDE_DACK1 SDTEST0 GPIO8 C31 CTS2 IDE_DREQ1 SDTEST4 GPIO9 C28 DCD2 IDE_IOW1 SDTEST2 GPIO10 B29 DSR2 IDE_IORDY1 SDTEST1 GPIO11 AJ8 RI2 IRQ15 GPIO12 N29 AB2C GPIO13 M29 AB2D GPIO14 D9 IOR...

Page 68: ...PD2 F_C BE0 D21 O ERR TFTD4 VOPD3 F_FRAME A22 O STB WRITE TFTD17 F_IRDY B20 O SLIN ASTRB TFTD16 F_STOP U29 O AC97_RST F_DEVSEL V31 O GPIO16 PC_BEEP F_GNT0 U31 O SDATA_IN F_TRDY U30 O BIT_CLK INTR_O D2...

Page 69: ...ST2 AJ1 O Internal Test Signals These signals are used for internal testing only For normal operation leave unconnected PLL5B TEST1 AG4 O PLL6B TEST0 AH3 O PLL2B GTEST F30 I Global Test This signal is...

Page 70: ...PCB AVCCTV D23 PWR 3 3V Analog TV DAC Power Connection Low noise power AVSSTV B24 GND Analog TV DAC Ground Connection Return current VBAT AL3 PWR Battery Provides battery back up to the RTC and ACPI r...

Page 71: ...e SC1200 SC1201 Processor Specification Update document Reserved bits in the General Configuration block should be read as written unless otherwise specified Table 4 1 General Configuration Block Regi...

Page 72: ...allel Port signals Fast PCI monitoring output signals can be enabled in two ways by setting this bit to 1 or by strapping FPCI_MON ball A4 high The strapped value can be read back at MCR 30 Listed bel...

Page 73: ...AC3 IDE_DATA0 TFTD6 A24 AC1 IDE_DATA1 TFTD16 D23 AC2 IDE_DATA2 TFTD14 C23 AB4 IDE_DATA3 TFTD12 B23 AB1 IDE_DATA4 FP_VDD_ON A23 AA4 IDE_DATA5 CLK27M C22 AA3 IDE_DATA6 IRQ9 B22 AA2 IDE_DATA7 INTD A21 Y3...

Page 74: ...TFTD1 PMR 15 0 and Note 1 F_AD6 Note 2 VOPD0 PMR 15 1 and Note 1 W1 B20 SLIN ASTRB Note 1 TFTD16 Note 1 F_IRDY Note 2 W2 C20 PD3 Note 1 TFTD9 Note 1 F_AD3 Note 2 W3 D20 PD2 Note 1 TFTD8 PMR 15 0 and N...

Page 75: ...P2CRSEL Select SP2 Flow Control Selects ball functions Ball 0 GPIO IDE Signals 1 Serial Port Signals Name Add l Dependencies Name Add l Dependencies AH4 C30 GPIO7 PMR 8 0 RTS2 PMR 8 0 IDE_DACK1 PMR 8...

Page 76: ...Port Signals Name Add l Dependencies Name Add l Dependencies J28 AK8 IRRX1 None SIN3 None J3 C11 IRTX None SOUT3 None 5 IOCS0SEL Select IOCS0 Selects ball function Works in conjunction with PMR 23 se...

Page 77: ...0ZWS Enable ZWS for IOCS0 Access This bit enables internal activation of ZWS Zero Wait States control for IOCS0 access 0 ZWS is not active for IOCS0 access 1 ZWS is active for IOCS0 access 10 DOCZWS E...

Page 78: ...PCI bus master is enabled use read modify write to ensure these bit contents are unchanged Offset 38h Interrupt Selection Register INTSEL R W Reset Value 00h This register selects the IRQ signal of th...

Page 79: ...A signal is 1 or The GX1 module s internal SUSPA signal is 0 and the WD32KPD bit Offset 02h 8 is 0 The 32 KHz input clock is disabled when The GX1 module s internal SUSPA signal is 0 and the WD32KPD b...

Page 80: ...ffset 00h 01h WATCHDOG Timeout Register WDTO R W Reset Value 0000h This register specifies the programmed WATCHDOG timeout period 15 0 Programmed timeout period Offset 02h 03h WATCHDOG Configuration R...

Page 81: ...clock is disabled when the GX1 module s inter nal SUSPA signal is 0 and the TM27MPD bit is 1 For more information about signal SUSPA see Section 4 4 2 1 Usage Hints on page 81 and the AMD Geode GX1 Pr...

Page 82: ...set 0Dh TIMER Configuration Register TMCNFG R W Reset Value 00h This register enables the High Resolution Timer interrupt selects the Timer clock and disables the 27 MHz internal clock during low powe...

Page 83: ...105 functional description of the RTC Figure 4 2 Clock Generation Block Diagram 32 768 KHz Crystal External PCI Clock PLL5 Internal Fast PCI Clock PLL6 ACPI Clock 14 318 MHz PLL2 Dot Clock Core Clock...

Page 84: ...and can vary from 0 to 10 pF The rule of thumb in choosing these capacitors is CL C1 C2 C1 C2 CPARASITIC Example 1 Crystal CL 10 pF CPARASITIC 8 2 pF C1 3 6 pF C2 3 6 pF Example 2 Crystal CL 20 pF CPA...

Page 85: ...SEL0 balls These can be read in the internal Fast PCI Clock field in the CCFC register GCB I O Offset 1Eh 9 8 See Table 4 8 on page 87 details on the CCFC register Note Not all speeds are supported Fo...

Page 86: ...es a 33 3 MHz clock that is created by PLL5 and divided by 2 PLL5 uses the 27 MHz clock to output a 66 67 MHz clock PLL5 has a frequency accuracy of 0 1 AC97 The SC1200 SC1201 processor generates the...

Page 87: ...Reserved 6 EXPCID Disable External PCI Clock 0 External PCI clock is enabled 1 External PCI clock is disabled 5 GPD Disable Graphic Pixel Reference Clock 0 PLL2 input clock is enabled 1 PLL2 input clo...

Page 88: ...that is used to generate the core clock These bits reflect the value of strap pins CLKSEL 1 0 00 33 3 MHz 01 48 MHz 10 66 7 MHz 11 33 3 MHz 7 4 Reserved 3 0 MVAL Multiplier Value This 4 bit value cont...

Page 89: ...C that provides RTC timekeeping Outstanding Features Full compatibility with ACPI Revision 1 0 requirements System Wakeup Control powered by VSB generates power up request and a PME power management e...

Page 90: ...f 4 0 Mbps FIR Selectable internal or external modulation demodula tion ASK IR and DASK IR options of SHARP IR Consumer IR TV Remote mode Consumer Remote Control supports RC 5 RC 6 NEC RCA and RECS 80...

Page 91: ...lug and Play ISA Specification Version 1 0a by Intel and Microsoft All sys tem resources assigned to the functional blocks I O address space DMA channels and IRQ lines are config ured in and managed b...

Page 92: ...ws the structure of the standard PnP config uration register file The SIO Control And Configuration registers are not banked and are accessed by the Index Data register pair only as described above Ho...

Page 93: ...ed after VSB is powered up The SIO module wakes up with the default setup as fol lows When a hardware reset occurs The configuration base address is 2Eh 15Ch or None according to the IO_SIOCFG_IN bit...

Page 94: ...e Configuration Registers Index 60h 75h These registers are used to manage the resource allocation to the functional blocks The I O port base address descriptor 0 is a pair of registers at Index 60h 6...

Page 95: ...ss bits 7 0 for I O Descriptor 0 Index 62h I O Port Base Address Bits 15 8 Descriptor 1 R W 7 0 Descriptor 1 A 15 8 Selects I O lower limit address bits 15 8 for I O Descriptor 1 Index 63h I O Port Ba...

Page 96: ...ne DMA channel 7 3 Reserved 2 0 DMA 1 Channel Select This bit field selects the DMA channel for DMA 1 The valid choices are 0 3 where a value of 0 selects DMA channel 0 1 selects channel 1 etc A value...

Page 97: ...cratch This bit controls bits 7 and 6 of this register Once this bit is set to 1 by software it can be cleared to 0 only by a hardware reset 0 Bits 7 and 6 of this register are R W bits Default 1 Bits...

Page 98: ...registers Table 5 6 Relevant RTC Configuration Registers Index Type Configuration Register or Action Reset Value 30h R W Activate When bit 0 is cleared the registers of this logical device are not ac...

Page 99: ...on the Extended RAM access Default 1 Writes to bytes 00h 1Fh of the Extended RAM are ignored 4 Block Extended RAM Read This bit controls read from bytes 00h 1Fh of the Extended RAM 0 No effect on Ext...

Page 100: ...nfiguration Register or Action Reset Value 30h R W Activate When bit 0 is cleared the registers of this logical device are not accessible 1 00h 60h R W Base Address MSB register 00h 61h R W Base Addre...

Page 101: ...02h Table 5 10 IRCP SP3 Configuration Register Bit Description Index F0h Infrared Communication Port Serial Port 3 Configuration Register R W Reset Value 02h 7 Bank Select Enable Enables bank switchi...

Page 102: ...04h 75h RO Report no DMA assignment 04h 04h F0h R W Serial Ports 1 and 2 Configuration register 02h 02h Table 5 12 Serial Ports 1 and 2 Configuration Register Bit Description Index F0h Serial Ports 1...

Page 103: ...on page 95 for descriptions of the oth ers Table 5 13 Relevant ACB1 and ACB2 Registers Index Type Configuration Register or Action Reset Value 30h R W Activate See also bit 0 of the SIOCF1 register 0...

Page 104: ...11 are RO 00000b Bit 2 for A10 should be 0b 02h 61h R W Base Address LSB register Bits 1 and 0 A1 and A0 are RO 00b For ECP Mode 4 EPP or when using the Extended registers bit 2 A2 should also be 0b...

Page 105: ...signal as the basic clock for timekeeping The 32 768 KHz clock can be sup plied by the internal oscillator circuit or by an external oscillator see Section 5 5 2 2 External Oscillator on page 106 5 5...

Page 106: ...2I of square or sine wave of 0 0V to VCORE amplitude The signal should have a duty cycle of approximately 50 It should be sourced from a battery backed source in order to oscillate during power down T...

Page 107: ...his mecha nism enables new time parameters to be loaded in the RTC Method 2 1 Access the RTC registers after detection of an Update Ended interrupt This implies that an update has just been completed...

Page 108: ...put power supply or VSB main battery To assure that the module uses power from VSB and not from VBAT the VSB voltage should be maintained above its minimum as detailed in Section 9 0 Electrical Specif...

Page 109: ...r off spurious bus transactions from the host may occur To protect the RTC internal regis ters from corruption all inputs are automatically locked out The lockout condition is asserted when VSB is low...

Page 110: ...m power down The RAMs are Standard RAM Extended RAM The memory maps and register content of the RAMs is provided in Section 5 5 4 RTC General Purpose RAM Map on page 115 The first 14 bytes and 3 progr...

Page 111: ...DOW Day Of Week Register VPP PUR 07h R W DOM Date Of Month Register VPP PUR 08h R W MON Month Register VPP PUR 09h R W YER Year Register VPP PUR 0Ah R W CRA RTC Control Register A Bit specific 0Bh R...

Page 112: ...est selection among other functions This register cannot be written before reading bit 7 of CRD 7 Update in Progress RO This bit is not affected by reset This bit reads 0 when bit 7 of the CRB Registe...

Page 113: ...n addition this bit is cleared to 0 when this register is read 0 No alarm detected since the last read 1 Alarm condition detected 4 Update Ended Interrupt Flag Cleared to 0 on RTC reset i e hardware o...

Page 114: ...122070 2 0 1 0 0 0 244141 3 0 1 0 1 0 488281 4 0 1 1 0 0 976562 5 0 1 1 1 1 953125 6 1 0 0 0 3 906250 7 1 0 0 1 7 812500 8 1 0 1 0 15 625000 9 1 0 1 1 31 250000 10 1 1 0 0 62 500000 11 1 1 0 1 125 00...

Page 115: ...M 2 Change the backup battery while normal operating power is present and not in backup mode to maintain valid time and register information If a low leakage capacitor is connected to VBAT the battery...

Page 116: ...on of matching can be used as a wakeup event The CEIR address detection operates independently of the serial port with the IR which is powered down with the rest of the system Whenever an IR signal is...

Page 117: ...set Type Name Reset Value 00h R W1C WKSR Wakeup Events Status Register 00h 01h R W WKCR Wakeup Events Control Register 03h 02h R W WKCFG Wakeup Configuration Register 00h Table 5 28 Bank 1 CEIR Wakeup...

Page 118: ...ction 0 Event not detected Default 1 Event detected Offset 01h Wakeup Events Control Register WKCR R W Reset Value 03h This register is set to 03h on power up of VPP or software reset Detected wakeup...

Page 119: ...Address Mask If the corresponding bit is 0 the address bit is not masked enabled for compare If the corresponding bit is 1 the address bit is masked ignored during compare Bank 1 Offset 07h CEIR Addr...

Page 120: ...rs are not used when the RC 5 protocol is selected NEC protocol The header pulse width must fall within this range in order for the header to be considered valid The nominal value is 9 msec for a 38 K...

Page 121: ...e Data is sampled during the high state of the serial clock ABC Consequently throughout the clock s high period the data should remain stable see Figure 5 13 Any changes on the ABD line during the hig...

Page 122: ...eceiver must pull down the ABD line during the ACK clock pulse signalling that it has cor rectly received the last data byte and is ready to receive the next byte Figure 5 16 illustrates the ACK cycle...

Page 123: ...7 6 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands Control of the bus is initially determined according to address bits and...

Page 124: ...et also check that ACBST 3 is cleared and clear it if required 2 Write the data byte to be transmitted to the ACBSDA When either ACBST 5 or ACBST 4 is set an interrupt is generated When the slave resp...

Page 125: ...e device continues to search the received message for a match If an address match or a global match is detected 1 The device asserts its ABD pin during the acknowl edge cycle 2 ACBCST 2 and ACBST 2 ar...

Page 126: ...ribed below This register maintains the current ACB status On reset and when the ACB is disabled ACBST is cleared 00h 7 SLVSTP Slave Stop R W1C Writing 0 to SLVSTP is ignored 0 Writing 1 or ACB disabl...

Page 127: ...art Condition or repeated Start and a Stop Condition including illegal Start or Stop Condition 1 In slave mode ACBCTL1 GCMEN is set and the address byte the first byte transferred after a Start Condit...

Page 128: ...er of the bus ACBST 1 1 setting START and then writing to ACBSDA generates a Start Condition If a transmission is already in progress a repeated Start Condition is generated This condition can be used...

Page 129: ...second level offsets EPP and second level offset registers are available only when the base address is 8 byte aligned Parallel Port functional block bit maps are shown in Table 5 35 and Table 5 36 Ta...

Page 130: ...ta 400h CFIFO Data Bits 400h DFIFO Data Bits 400h TFIFO Data Bits 400h CNFGA RSVD Bit 7 of PP Confg0 RSVD 401h CNFGB RSVD Interrupt Request Value Interrupt Select RSVD DMA Channel Select 402h ECR ECP...

Page 131: ...and SP2 Register and Bit Maps for UART Functionality The tables in this subsection provide register and bit maps for Banks 0 through 3 Figure 5 18 UART Mode Register Bank Architecture Bank 0 Bank 1 Ba...

Page 132: ...l R W BSR1 Bank Select 04h 07h RSVD Reserved 1 When bit 7 of this register is set to 1 bits 6 0 of BSR select the bank as shown in Table 5 38 on page 132 Table 5 40 Bank 2 Register Map Offset Type Nam...

Page 133: ...R1 RSVD LOOP ISEN or DCDLP RILP RTS DTR MCR2 RSVD TX_DFR RSVD RTS DTR 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS 07h SPR1 Scratch Data ASCR2 RSVD TXUR4 RXA...

Page 134: ...ST RSVD ETDLBK LOOP RSVD EXT_SL 03h BSR BKSE BSR 6 0 Bank Select 04h EXCR2 LOCK RSVD PRESL 1 0 RSVD 05h RSVD Reserved 06h RXFLV RSVD RFL 4 0 07h TXFLV RSVD TFL 4 0 Table 5 45 Bank 3 Bit Map Register B...

Page 135: ...ining eight registers con trol IR SP3 operation All registers use the same 8 byte address space to indicate offsets 00h through 07h The BSR register selects the active bank and is common to all banks...

Page 136: ...W LBGD L Legacy Baud Generator Divisor Port Low Byte 01h R W LBGD H Legacy Baud Generator Divisor Port High Byte 02h RSVD Reserved 03h W LCR1 Link Control R W BSR1 Bank Select 04h 07h RSVD Reserved 1...

Page 137: ...yte RO TFRCC L Transmission Current Count Low Byte 05h R W TFRL H Transmission Frame Length High Byte RO TFRCC H Transmission Current Count High Byte 06h R W RFRML L Reception Frame Maximum Length Low...

Page 138: ...Table 5 55 Bank 0 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h RXD RXD 7 0 Receive Data TXD TXD 7 0 Transmit Data 01h IER1 RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER2 TMR_IE SFIF_IE TXEMP_ IE PL...

Page 139: ...Select 04h EXCR2 LOCK RSVD PRESL 1 0 RF_SIZ 1 0 TF_SIZ 1 0 05h RSVD RSVD 06h TXFLV RSVD TFL 5 0 07h RXFLV RSVD RFL 5 0 Table 5 58 Bank 3 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h MID MID 3...

Page 140: ...D MAX_LEN PHY_ERR BAD_CRC OVR1 OVR2 06h RFRL L LSTFRC RFRL 7 0 Low Byte Data LSTFRC 7 0 07h RFRL H RFRL 15 8 High Byte Data Table 5 61 Bank 6 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h IRCR...

Page 141: ...Bus Three independent USB interfaces Open Host Controller Interface OpenHCI specification compliant PCI Interface PCI 2 1 compliant PCI master for AC97 and IDE controllers Subtractive agent for unclai...

Page 142: ...face Low Pin Count LPC Interface Based on Intel LPC Interface Specification Revision 1 0 Serial IRQ support 6 2 Module Architecture The Core Logic architecture provides the internal functional blocks...

Page 143: ...ISA or legacy DMA masters These memory cycles are always forwarded to the Fast PCI interface 6 2 1 4 External PCI Bus The external PCI bus is a fully compliant PCI bus PCI slots are connected to this...

Page 144: ...6 2 3 2 PIO Mode The IDE data port transaction latency consists of address latency asserted latency and recovery latency Address latency occurs when a PCI master cycle targeting the IDE data port is...

Page 145: ...gister These registers and bit formats are described in Table 6 36 on page 260 Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descrip...

Page 146: ...Core Logic and the IDE via providing data toggling STROBE and DMARDY The IDE_DATA 15 0 is latched by receiver on each rising and falling edge of STROBE The transmitter can pause the burst cycle by hol...

Page 147: ...ctive DOCR is active otherwise it is inactive DOCW DOCW is asserted on memory write transactions to DOCCS window i e when both DOCCS and MEMW are active DOCW is active otherwise it is inactive RD WR T...

Page 148: ...tween a PCI cycle and the corresponding ISA cycle generated Note Not all signals described in Figure 6 2 are available externally See Section 3 4 8 Sub ISA Interface Signals on page 59 for more inform...

Page 149: ...registers on the on chip I O data bus When PCI data bus drivers of the Core Logic module are in TRI STATE data transfers between the PCI bus master and PCI bus devices are handled directly via the PCI...

Page 150: ...it sends a bus grant request to the PCI arbiter After the PCI bus has been granted the respective DACK is driven active The Core Logic module generates PCI memory read or write cycles in response to a...

Page 151: ...r to reduce the number of balls on the device Cycle multiplex ing is on a bus cycle by bus cycle basis see Figure 6 6 on page 152 where the internal Core Logic PCI bridge arbi trates between PCI cycle...

Page 152: ...Note DMA interface signals are not available externally DMA Channels The Core Logic module supports seven DMA channels using two standard 8237 equivalent controllers DMA Con troller 1 contains Channel...

Page 153: ...e types of transfers read write or ver ify The transfer type selected defines the method used to transfer a byte or WORD during one DMA bus cycle For read transfer types the Core Logic module reads da...

Page 154: ...be set up by the system before a DMA operation The DMA Page register values are driven on PCI address bits AD 31 16 for 8 bit channels and AD 31 17 for 16 bit channels The middle address portion whic...

Page 155: ...ed with GPIO39 function See Table 6 4 The Core Logic module allows PCI interrupt signals INTA INTB INTC muxed with GPIO19 IOCHRDY and INTD muxed with IDE_DATA7 to be routed internally to any IRQ signa...

Page 156: ...pt controller should be programmed with the value 02h slave ID and corresponds to the input on the master controller PIC Shadow Register The PIC registers are shadowed to allow for 0V Suspend to save...

Page 157: ...e an SMI for an NMI Note that NMI is not a pin 6 2 8 Keyboard Support The Core Logic module can actively decode the keyboard controller I O Ports 060h 062h 064h and 066h and gener ate an LPC bus cycle...

Page 158: ...It also supports systems with an external micro controller that is used as a power management controller 6 2 9 1 CPU States The SC1200 SC1201 processor supports three CPU states C0 C1 and C3 the Core...

Page 159: ...erformed when exiting this state The SC1200 SC1201 processor keeps all context in this state This state corresponds to ACPI sleep state S1 with lower power and longer wake time than in SL1 SL3 Sleep S...

Page 160: ...power manage ment events that can manage Transition of the system from a Sleep state to a Work state This is done by the hardware These events are defined as wakeup events Enabled wakeup events to se...

Page 161: ...nd a wakeup event or an inter rupt is generated note that this is regardless of the PWRBTN_EN bit F1BAR1 I O Offset 0Ah 8 Power Button Sleep Event Detection of a high to low transition on the debounce...

Page 162: ...and is dis cussed in Section 6 2 10 3 Peripheral Power Management on page 164 APM if available is used primarily by CPU power manage ment since the operating system is most capable of report ing the...

Page 163: ...Offset 08h The SMI Speedup Disable register prevents VSA software from entering Suspend Modulation while operating in SMM The data read from this register can be ignored If the Suspend Modulation feat...

Page 164: ...these timers are F0 Index 81h 7 Video Access Idle Timer Enable F0 Index 82h 7 Video Access Trap Enable F0 Index A6h 15 0 Video Timer Count F0 Index 83h 3 VGA Timer Enable F0 Index 8Bh 6 VGA Timer Base...

Page 165: ...I status reporting The sec ond level of SMI status reporting is set up very much like the top level There are two status reporting registers one read only mirror and one read to clear The data returne...

Page 166: ...d Device 1 Idle Timer 81h 4 A0h 15 0 C0h 31 0 CCh 7 0 85h 4 F5h 4 User Defined Device 2 Idle Timer 81h 5 A2h 15 0 C4h 31 0 CDh 7 0 85h 5 F5h 5 User Defined Device 3 Idle Timer 81h 6 A4h 15 0 C8h 31 0...

Page 167: ...O Port 2F8h 2FFh or COM4 I O Port 2E8h 2EFh Support trapping for low I O Port 00h 0Fh and or high I O Port C0h DFh DMA accesses Support hardware status register reads in Core Logic module minimizing...

Page 168: ...address of the JMP The target address must be on a 32 byte boundary so bits 4 0 must be written to 0 There is no data transfer with this PRD This PRD allows the creation of a looping mechanism If a P...

Page 169: ...nted by 08h and is now pointing to PRD_3 The SMI Status register is read to clear the End of Page status flag Since Audio Buffer_1 is now empty the software can refill it At the completion of PRD_2 an...

Page 170: ...Control Registers The codec 32 bit related registers GPIO Status and Control Registers Codec GPIO Status Register F3BAR0 Memory Offset 00h Codec GPIO Control Register F3BAR0 Memory Offset 04h Codec St...

Page 171: ...Mirror and Status registers are the top level of hierarchy for the SMI Handler in determining the source of an SMI These two registers are at F1BAR0 Memory Offset 00h Status Mirror and 02h Sta tus Th...

Page 172: ...determine top level source of SMI F3BAR0 Memory Offset 10h Read to Clear SMI de asserted after all SMI Sources are Cleared Bit 7 ABM5_SMI Bits 15 2 Bit 0 Bit 1 AUDIO_SMI Offset 02h Module to determin...

Page 173: ...refer to the LPC specification directly The goals of the LPC interface are to Enable a system without an ISA bus Reduce the cost of traditional ISA bus devices Use on a motherboard only Perform the s...

Page 174: ...Use PCI 33 MHz clock signal PCICLK instead Core Logic module optional LPC signals LDRQ Encoded DMA Bus Master Request Only needed by peripheral that need DMA or bus mastering Peripherals may not share...

Page 175: ...e Configuration Data Register CDR To access PCI configuration space write the Configuration Address 0CF8h Register with data that specifies the Core Logic module as the device on PCI being accessed al...

Page 176: ...O mapped GPIO Runtime and Configuration Registers sum marized in Table 6 15 00000001h Page 192 14h 17h 32 R W Base Address Register 1 F0BAR1 Sets the base address for the I O mapped LPC Configuration...

Page 177: ...ter 00h Page 212 8Eh 8 R W VGA Timer Count Register 00h Page 213 8Fh 92h Reserved 00h Page 213 93h 8 R W Miscellaneous Device Control Register 00h Page 213 94h 95h 16 R W Suspend Modulation Register 0...

Page 178: ...User Defined Device 1 Control Register 00h Page 219 CDh 8 R W User Defined Device 2 Control Register 00h Page 219 CEh 8 R W User Defined Device 3 Control Register 00h Page 219 CFh Reserved 00h Page 2...

Page 179: ...W GPIO Signal Configuration Select Register 00000000h Page 225 24h 27h 32 R W GPIO Signal Configuration Access Register 00000044h Page 226 28h 2Bh 32 R W GPIO Reset Control Register 00000000h Page 227...

Page 180: ...eserved 00h Page 236 40h 43h 32 R W Base Address Register 1 F1BAR1 Sets the base address for the I O mapped ACPI Support Registers summarized in Table 6 19 00000001h Page 236 44h FFh Reserved 00h Page...

Page 181: ...0000h Page 248 0Ah 0Bh 16 R W PM1A_EN PM1A Enable Register 0000h Page 249 0Ch 0Dh 16 R W PM1A_CNT PM1A Control Register 0000h Page 249 0Eh 8 R W ACPI_BIOS_STS Register 00h Page 250 0Fh 8 R W ACPI_BIOS...

Page 182: ...ule 00000000h Page 256 18h 1Bh 32 RO Base Address Register 2 F2BAR2 Reserved for possible future use by the Core Logic module 00000000h Page 256 1Ch 1Fh 32 RO Base Address Register 3 F2BAR3 Reserved f...

Page 183: ...Header Registers for Audio Support Summary F3 Index Width Bits Type Name Reset Value Reference Table 6 37 00h 01h 16 RO Vendor Identification Register 100Bh Page 262 02h 03h 16 RO Device Identificatio...

Page 184: ...h Not Used Page 271 24h 27h 32 R W Audio Bus Master 0 PRD Table Address 00000000h Page 271 28h 8 R W Audio Bus Master 1 Command Register 00h Page 272 29h 8 RC Audio Bus Master 1 SMI Status Register 00...

Page 185: ...future use by the Core Logic module 00000000h Page 278 20h 23h 32 R W Base Address Register 4 F5BAR4 Reserved for possible future use by the Core Logic module 00000000h Page 278 24h 27h 32 R W Base Ad...

Page 186: ...Page 284 0Ch 8 R W Cache Line Size 00h Page 284 0Dh 8 R W Latency Timer 00h Page 284 0Eh 8 RO Header Type 00h Page 284 0Fh 8 RO BIST Register 00h Page 284 10h 13h 32 R W Base Address 0 00000000h Page...

Page 187: ...e 288 28h 2Bh 32 R W HcBulkHeadED 00000000h Page 288 2Ch 2Fh 32 R W HcBulkCurrentED 00000000h Page 288 30h 33h 32 R W HcDoneHead 00000000h Page 288 34h 37h 32 R W HcFmInterval 00002EDFh Page 288 38h 3...

Page 188: ...ster Not Used Page 298 0C4h R W DMA Channel 5 Address Register Page 298 0C6h R W DMA Channel 5 Transfer Count Register Page 298 0C8h R W DMA Channel 6 Address Register Page 298 0CAh R W DMA Channel 6...

Page 189: ...h WO Master Slave PIC OCW2 Page 305 020h 0A0h WO Master Slave PIC OCW3 Page 305 020h 0A0h RO Master Slave PIC Interrupt Request and Service Registers for OCW3 Commands Page 305 Keyboard Controller Reg...

Page 190: ...they are read a byte at a time status bits may be lost or not cleared 6 4 1 Bridge GPIO and LPC Registers Function 0 The register space designated as Function 0 F0 is used to configure Bridge feature...

Page 191: ...t is set whenever a master abort cycle occurs A master abort occurs when a PCI cycle is not claimed except for special cycles Write 1 to clear 12 Received Target Abort This bit is set whenever a targe...

Page 192: ...r RO Reset Value 00h This register indicates various information about the PCI Built In Self Test BIST mechanism Note This mechanism is not supported in the Core Logic module in the SC1200 SC1201 proc...

Page 193: ...O Offset 00h 02h 9 Second level SMI status is reported at F1BAR0 I O Offset 04h 06h 5 4 Video Configuration Trap If this bit is set to 1 and an access occurs to one of the configuration registers in P...

Page 194: ...ble PCI Delayed Transactions for Access to I O Address 1F0h 1F7h Primary IDE Channel PIO mode uses repeated I O transactions that are faster when non delayed transactions are used 0 I O addresses comp...

Page 195: ...y for clock configuration at power up Index 45h Reserved Reset Value 00h Index 46h PCI Functions Enable Register R W Reset Value FEh 7 6 Reserved Resets to 11 5 F5 PCI Function 5 When asserted set to...

Page 196: ...0 to pass to IRQ0 3 PIT Counter 0 Enable 0 Sets GATE0 input low 1 Sets GATE0 input high 2 0 ISA Clock Divisor Determines the divisor of the PCI clock used to make the ISA clock which is typically prog...

Page 197: ...rites to the configured ROM space asserts ROMCS enabling the write cycle to the Flash device on the ISA bus Otherwise ROMCS is inhibited for writes If strapped for LPC and this bit is set to 1 the cyc...

Page 198: ...ports 2F8h 2FFh 0 Subtractive 1 Positive 2 COM1 Positive Decode Selects PCI positive or subtractive decoding for accesses to I O ports 3F8h 3FFh 0 Subtractive 1 Positive 1 Keyboard Controller Positiv...

Page 199: ...for signals INTB and INTA Note The target interrupt must first be configured as level sensitive via I O Ports 4D0h and 4D1h in order to maintain PCI interrupt compatibility 7 4 INTB Ball C26 Target In...

Page 200: ...active 2 ACPI C3 SUSP_3V Enable Allow internal SUSP_3V to be active during C3 state 0 Disable 1 Enable 1 ACPI SL1 SUSP_3V Enable Allow internal SUSP_3V to be active during SL1 sleep state 0 Disable 1...

Page 201: ...ss register 7 I O Chip Select 0 Positive Decode IOCS0 0 Disable 1 Enable 6 Writes Result in Chip Select When this bit is set to 1 writes to configured I O address base address configured in F0 Index 7...

Page 202: ...a configurable duration when system is power managed using CPU Suspend modulation 0 Disable 1 Enable The duration of the speedup is configured in the Video Speedup Timer Count Register F0 Index 8Dh De...

Page 203: ...ccurs in the programmed address range the timer is reloaded with the programmed count UDEF2 address programming is at F0 Index C4h base address register and CDh control register Top level SMI status i...

Page 204: ...Timer Enable Turn on Floppy Disk Idle Timer Count Register F0 Index 9Ah and generate an SMI when the timer expires 0 Disable 1 Enable If an access occurs in the address ranges listed below the timer i...

Page 205: ...User Defined Device 1 UDEF1 Access Trap If this bit is enabled and an access occurs in the programmed address range an SMI is generated UDEF1 address programming is at F0 Index C0h base address regis...

Page 206: ...l SMI status is reported at F1BAR0 I O Offset 00h 02h 0 Second level SMI status is reported at F0 Index 86h F6h 4 6 Secondary Hard Disk Access Trap If this bit is enabled and an access occurs in the a...

Page 207: ...at F1BAR0 I O Offset 00h 02h 9 Second level SMI status is reported at F1BAR0 I O Offset 04h 06h 0 Index 84h Second Level PME SMI Status Mirror Register 1 RO Reset Value 00h The bits in this register...

Page 208: ...evice 2 Idle Timer Count Register F0 Index A2h 0 No 1 Yes To enable SMI generation set F0 Index 81h 5 to 1 4 User Defined Device Idle Timer 1 Timeout Indicates whether or not an SMI was caused by expi...

Page 209: ...Index 83h 6 to 1 4 Secondary Hard Disk Idle Timer SMI Status Indicates whether or not an SMI was caused by expiration of Secondary Hard Disk Idle Timer Count register F0 Index ACh 0 No 1 Yes To enable...

Page 210: ...IR To enable SMI generation set F1BAR1 I O Offset 0Ch 0 to 0 2 Codec SDATA_IN SMI Status Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on SDATA_IN 0 No 1 Yes To en...

Page 211: ...ouse I O address range listed below reloads General Purpose Timer 1 Keyboard Controller I O Ports 060h 064h COM1 I O Port 3F8h 3FFh if F0 Index 93h 1 0 10 this range is included COM2 I O Port 2F8h 2FF...

Page 212: ...Shift GP Timer 1 is treated as an 8 bit or 16 bit timer 0 8 bit The count value is that loaded into GP Timer 1 Count Register F0 Index 88h 1 16 bit The value loaded into GP Timer 1 Count Register is...

Page 213: ...and 177h 3 2 Reserved Must be set to 0 1 Mouse on Serial Enable Mouse is present on a Serial Port 0 No 1 Yes If a mouse is attached to a serial port i e this bit is set to 1 that port is removed from...

Page 214: ...t in use so that it can be powered down The 16 bit value programmed here represents the period of hard disk inactivity after which the sys tem is alerted via an SMI The timer is automatically reloaded...

Page 215: ...F0 Index 81h 5 1 Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 0 Second level SMI status is reported at F0 Index 85h F5h 5 Index A4h A5h User Defined Device 3 Idle Timer Count Registe...

Page 216: ...l system clocks Upon a Resume event the internal SUSP_3V signal is de asserted After a slight delay the Core Logic module de asserts the SUSP signal Once the clocks are stable the GX1 module de assert...

Page 217: ...ter Each shadow register in the sequence contains the last data written to that location The read sequence for this register is 1 PIC1 ICW1 2 PIC1 ICW2 3 PIC1 ICW3 4 PIC1 ICW4 Bits 7 5 of ICW4 are alw...

Page 218: ...which allows the clock chip and GX1 module PLL to stabilize before de asserting the internal SUSP signal Index BDh BFh Reserved Reset Value 00h Index C0h C3h User Defined Device 1 Base Address Regist...

Page 219: ...Bits 4 0 Mask for address bits A 4 0 If bit 7 1 Memory Bits 6 0 Mask for address memory bits A 15 9 512 bytes min and 64 KB max A 8 0 are ignored Note A 1 in a mask bit means that the address bit is i...

Page 220: ...F1BAR1 I O Offset 15h 5 to 1 to allow SMI generation 0 GPWIO0 SMI Status Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin 0 No 1 Yes To enable SMI generation 1 Ensure that...

Page 221: ...e Timer Count Register F0 Index 98h 0 No 1 Yes To enable SMI generation set F0 Index 81h 0 1 Index F6h Second Level PME SMI Status Register 3 RC Reset Value 00h The bits in this register contain secon...

Page 222: ...7 which has a third level of status reporting at F0BAR0 I O 0Ch 1Ch A read only Mirror version of this register exists at F0 Index 87h If the value of the register must be read without clearing the S...

Page 223: ...dicates whether or not an SMI was caused by an RTC interrupt 0 No 1 Yes This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs and F1BAR1 I O Offset 0Ch 0 0 0 ACPI Timer SMI Sta...

Page 224: ...gh Offset 08h 0Bh GPIEN0 GPIO Interrupt Enable 0 Register R W Reset Value 00000000h 31 16 Reserved Must be set to 0 15 0 GPIO Power Management Event PME Enable Bits 15 0 correspond to GPIO15 GPIO0 sig...

Page 225: ...orresponding GPIO signal 0 Disable PME generation 1 Enable PME generation Notes 1 All of the enabled GPIO PMEs are always reported at F1BAR1 I O Offset 10h 3 2 Any enabled GPIO PME can be selected to...

Page 226: ...ll Y3 111000 GPIO56 101001 GPIO41 ball W4 111001 GPIO57 101010 GPIO42 111010 GPIO58 101011 GPIO43 111011 GPIO59 101100 GPIO44 111100 GPIO60 101101 GPIO45 111101 GPIO61 101110 GPIO46 111110 GPIO62 1011...

Page 227: ...nal pull up capability of the selected GPIO signal It supports open drain output signals with internal pull ups and TTL input signals 0 Disable 1 Enable Default Bits 1 0 of this register must 01 for t...

Page 228: ...NTD signal 0 PCI INTD ball AA2 1 LPC SERIRQ ball J31 19 INTC Source Selects the interface source of the INTC signal 0 PCI INTC ball C9 1 LPC SERIRQ ball J31 18 INTB Source Selects the interface source...

Page 229: ...elects the interface source of the IRQ0 signal 0 ISA IRQ0 Internal signal Connected to OUT0 System Timer of the internal 8254 PIT 1 LPC SERIRQ ball J31 Offset 04h 07h SERIRQ_LVL Serial IRQ Level Contr...

Page 230: ...interface source for IRQ9 F0BAR1 I O Offset 00h 9 1 this bit allows signal polarity selection 0 Active high 1 Active low 8 IRQ8 Polarity If LPC is selected as the interface source for IRQ8 F0BAR1 I O...

Page 231: ...1 24 frames 1011 28 frames 1111 32 frames 1 0 Start Frame Pulse Width 00 4 Clocks 01 6 Clocks 10 8 Clocks 11 Reserved Offset 0Ch 0Fh DRQ_SRC DRQ Source Register R W Reset Value 00000000h Note DRQx are...

Page 232: ...uted to LPC when using the internal SuperI O module and if IO_SIOCFG_IN F5BAR0 I O Offset 00h 26 25 10 12 LPC Ad Lib Addressing Ad Lib addresses I O Ports 388h 389h See bit 16 for decode 11 LPC ACPI A...

Page 233: ...O Offset 10h 6 13 12 LPC Microsoft Sound System MSS Address Select Selects I O Port 00 530h 537h 10 E80h E87h 01 604h 60Bh 11 F40h F47h Selected address range is enabled via F0BAR1 I O Offset 10h 5 11...

Page 234: ...AR0 I O Offset 02h 3 Second level status is reported at bit 6 of this register 8 SMI Configuration for LPC Error Enable Allows LPC errors to generate an SMI 0 Disable 1 Enable Top Level SMI status is...

Page 235: ...ng a write operation on LPC 0 No 1 Yes Write 1 to clear 1 LPC Error DMA Status Indicates whether or not an error was generated during a DMA operation on LPC 0 No 1 Yes Write 1 to clear 0 LPC Error Mem...

Page 236: ...ster RO Reset Value 068000h Index 0Ch PCI Cache Line Size Register RO Reset Value 00h Index 0Dh PCI Latency Timer Register RO Reset Value 00h Index 0Eh PCI Header Type RO Reset Value 00h Index 0Fh PCI...

Page 237: ...Command Indicates whether or not an SMI was caused by a Warm Reset command 0 No 1 Yes 12 SMI Source is NMI Indicates whether or not an SMI was caused by NMI activity 0 No 1 Yes 11 SMI Source is IRQ2...

Page 238: ...xcept for GP timers UDEFx and PCI ISA function traps that are reported in bit 9 0 No 1 Yes The next level second level of SMI status is at F0 Index 84h F4h 87h F7h Offset 02h 03h Top Level PME SMI Sta...

Page 239: ...0 No 1 Yes 7 SMI on an A20M Toggle Read to Clear Indicates whether or not an SMI was caused by an access to either Port 92h or the keyboard command which initiates an A20M SMI 0 No 1 Yes This method...

Page 240: ...access to ISA Legacy I O register space set F0 Index 41h 0 1 Trapped access to F1 register space set F0 Index 41h 1 1 Trapped access to F2 register space set F0 Index 41h 2 1 Trapped access to F3 reg...

Page 241: ...41h 2 1 Trapped access to F3 register space set F0 Index 41h 3 1 Trapped access to F4 register space set F0 Index 41h 4 1 Trapped access to F5 register space set F0 Index 41h 5 1 4 SMI Source is Trap...

Page 242: ...s register does not clear the SMI For more information see F1BAR0 I O Offset 22h 15 6 Reserved Always reads 0 5 ACPI BIOS SMI Status Indicates whether or not an SMI was caused by ACPI software raising...

Page 243: ...O Offset 0Ch 13 0 No 1 Yes To enable SMI generation set F1BAR1 I O Offset 18h 9 to 1 default 1 THT_EN SMI Status Indicates whether or not an SMI was caused by a write of 1 to the ACPI THT_EN bit F1BA...

Page 244: ...No 1 Yes To enable SMI generation set bit 1 to 1 16 EXT_SMI0 SMI Status Read to Clear Indicates whether or not an SMI was caused by an assertion of EXT_SMI0 0 No 1 Yes To enable SMI generation set bi...

Page 245: ...I5 SMI Enable When this bit is asserted allow EXT_SMI5 to generate an SMI on negative edge events 0 Disable 1 Enable Top level SMI status is reported at F1BAR0 00h 02h 10 Second level SMI status is re...

Page 246: ...I status is reported at bits 16 RC and 8 RO Offset 28h 4Fh Not Used Reset Value 00h Offset 50h FFh The I O mapped registers located here F1BAR0 I O Offset 50h FFh can also be accessed at F0 Index 50h...

Page 247: ...for an SMI any SMI to be generated and serviced before transfer into C3 power state A read of this register causes an SMI if enabled F1BAR1 I O Offset 18h 11 1 default Top level SMI status is reporte...

Page 248: ...SCI generation is always enabled Write 1 to clear 10 RTC_STS Real Time Clock Status Indicates if a Power Management Event PME was caused by the RTC generating an alarm RTC IRQ signal is asserted 0 No...

Page 249: ...be set F1BAR1 I O Offset 0Ch 0 1 The SCIs enabled via this register are globally enabled by setting F1BAR1 I O Offset 08h There is no second level of SCI status report ing for these bits 15 11 Reserv...

Page 250: ...an SMI set BIOS_EN F1BAR1 I O Offset 0Fh 0 to 1 The top level SMI status is reported at F1BAR0 I O offset 00h 02h Second level status is at F1BAR0 I O Offset 22h 5 1 BM_RLD Bus Master RLD If the proce...

Page 251: ...erates an SMI and the status is reported in F1BAR0 00h 02h 0 9 GPWIO1_STS Indicates if PME was caused by activity on GPWIO1 0 No 1 Yes Write 1 to clear For the PME to generate an SCI 1 Ensure that GPW...

Page 252: ...event from the SuperI O module 0 No 1 Yes Write 1 to clear For the PME to generate an SCI set F1BAR1 I O Offset 12h 0 1 and F1BAR1 I O Offset 0Ch 0 1 See Note 2 in the general description of this regi...

Page 253: ...ned as any of the following events activities Modem Telephone Keyboard Mouse CEIR Consumer Electronic Infrared Offset 14h GPWIO Control Register 1 R W Reset Value 00h 7 4 Reserved Must be set to 0 3 R...

Page 254: ...direction of GPWIO2 0 Input 1 Output 1 GPWIO1_DIR Selects the direction of GPWIO1 0 Input 1 Output 0 GPWIO0_DIR Selects the direction of the GPWIO0 0 Input 1 Output Offset 16h GPWIO Data Register R W...

Page 255: ...on when the THT_EN bit F1BAR1 I O Offset 00h 4 is set 0 Disable 1 Enable Default Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 2 Second level SMI status is reported at F1BAR0 I O Offse...

Page 256: ...06h 07h PCI Status Register RO Reset Value 0280h Index 08h Device Revision ID Register RO Reset Value 01h Index 09h 0Bh PCI Class Code Register RO Reset Value 010180h Index 0Ch PCI Cache Line Size Re...

Page 257: ...le 3 0 t1 Address Setup Time value 1 cycle If Index 44h 31 1 Format 1 Bits 31 0 allow independent timing control of command and data Format 1 settings for a Fast PCI clock frequency of 33 3 MHz PIO Mo...

Page 258: ...very time 4 bit value 1 cycle 7 4 tDW IDE_IOW pulse width value 1 cycle 3 0 tM IDE_CS 1 0 to IDE_IOR IOW setup IDE_CS 1 0 setup to IDE_DACK0 DACK1 If bit 20 1 UltraDMA Settings for a Fast PCI clock fr...

Page 259: ...x 40h for bit descriptions Index 54h 57h Channel 1 Drive 0 DMA Control Register R W Reset Value 00077771h Channel 1 Drive 0 MDMA UDMA Control Register See F2 Index 44h for bit descriptions Note The PI...

Page 260: ...transferred from the drive is dis carded This bit should be reset after completion of data transfer Offset 01h Not Used Offset 02h IDE Bus Master 0 Status Register Primary R W Reset Value 00h 7 Simpl...

Page 261: ...y R W Reset Value 00h 7 Reserved Read Only 6 Drive 1 DMA Capable Allow Drive 1 to perform DMA transfers 0 Disable 1 Enable 5 Drive 0 DMA Capable Allow Drive 0 to perform DMA transfers 0 Disable 1 Enab...

Page 262: ...isable 1 Enable This bit must be enabled to access memory offsets through F3BAR0 See F3 Index 10h 0 Reserved Read Only Index 06h 07h PCI Status Register RO Reset Value 0280h Index 08h Device Revision...

Page 263: ...h 07h Codec GPIO Control Register R W Reset Value 00000000h 31 20 Reserved Must be set to 0 19 0 Codec GPIO Pin Data This field indicates the GPIO pin data that is sent to the codec in slot 12 on the...

Page 264: ...Level Audio SMI Status Register RC Reset Value 0000h The bits in this register contain second level SMI status reporting Top level is reported at F1BAR0 I O Offset 00h 02h 1 Reading this register cle...

Page 265: ...ap 0 No 1 Yes The next level third level of SMI status reporting is at F3BAR0 Memory Offset 14h Offset 12h 13h Second Level Audio SMI Status Mirror Register RO Reset Value 0000h Note The bits in this...

Page 266: ...ates if an SMI was caused by an I O trap 0 No 1 Yes The next level third level of SMI status reporting is at F3BAR0 Memory Offset 14h Offset 14h 17h I O Trap SMI and Fast Write Status Register RO RC R...

Page 267: ...F1BAR0 I O Offset 00h 02h 1 SMI generation enabling is at F3BAR0 Memory Offset 18h 2 9 0 X Bus Address Read Only This bit field contains the captured ten bits of X Bus address Offset 18h 19h I O Trap...

Page 268: ...address ranges selected by bits 1 0 an SMI is gen erated 0 Disable 1 Enable Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 1 Second level SMI status is reported at F3BAR0 Memory Offset...

Page 269: ...xternal 1 Internal 0 Reserved Must be set to 0 Offset 1Ch 1Fh Internal IRQ Control Register R W Reset Value 00000000h Note Bits 31 16 of this register are Write Only Reads to these bits always return...

Page 270: ...ternal IRQ14 0 Disable 1 Enable 13 Reserved Set to 0 12 Assert Masked Internal IRQ12 0 Disable 1 Enable 11 Assert masked internal IRQ11 0 Disable 1 Enable 10 Assert Masked Internal IRQ10 0 Disable 1 E...

Page 271: ...s Master Error Indicates if hardware encountered a second EOP before software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it...

Page 272: ...encountered a second EOP before software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it causes the bus master to pause until...

Page 273: ...software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it causes the bus master to pause until this register is read to clear t...

Page 274: ...nd EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause until this register is read to c...

Page 275: ...tes if hardware encountered a second EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to paus...

Page 276: ...ware encountered a second EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause until thi...

Page 277: ...are defined as allowing access to I O mapped registers this bit must be set to 1 BAR configuration is programmed through the corre sponding mask register see F5 Index 40h 44h 48h 4Ch 50h and 54h Index...

Page 278: ...4 Address Mask Determines the size of the BAR Every bit that is a 1 is programmable in the BAR Every bit that is a 0 is fixed 0 in the BAR Since the address mask goes down to bit 4 the smallest memor...

Page 279: ...er above for bit descriptions Note Whenever a value is written to this mask register F5BAR5 must also be written even if the value for F5BAR5 has not changed Index 58h F5BARx Initialized Register R W...

Page 280: ...Interface Function 5 32579B Index 64h 67h Scratchpad Usually used for Configuration Block Address R W Reset Value 00000000h BIOS writes a value of the Configuration Block Address Index 68h FFh Reserve...

Page 281: ...ated SIO ISA Bus Control Allow the integrated SIO to drive the internal ISA bus 0 Disable 1 Enable Default 23 21 Reserved Set to 0 20 IO_USB_SMI_PWM_EN USB Internal SMI Route USB generated SMI to SMI...

Page 282: ...ct to the voltage adjustment interface on the three USB transceivers Default 100 12 8 IO_USB_XCVT_CADJ USB Current Adjustment These bits connect to the current adjustment interface on the three USB tr...

Page 283: ...Device Identification Register RO Reset Value A0F8h Index 04h 05h Command Register R W Reset Value 00h 15 10 Reserved Must be set to 0 9 Fast Back to Back Enable Read Only USB only acts as a master t...

Page 284: ...ndex 08h Device Revision ID Register RO Reset Value 08h Index 09h 0Bh PCI Class Code Register RO Reset Value 0C0310h This register identifies the generic function of the USB the specific register leve...

Page 285: ...x 40h 43h ASIC Test Mode Enable Register R W Reset Value 000F0000h Used for internal debug and test purposes only Index 44h ASIC Operational Mode Enable Register R W Reset Value 00h 7 1 Write Only Rea...

Page 286: ...by software this bit sets the OwnershipChange field in HcInterruptStatus The bit is cleared by software 2 BulkListFilled Set to indicate there is an active ED on the Bulk List The bit may be set by e...

Page 287: ...neration due to Start of Frame 1 WritebackDoneHeadEnable 0 Ignore 1 Enable interrupt generation due to Writeback Done Head 0 SchedulingOverrunEnable 0 Ignore 1 Enable interrupt generation due to Sched...

Page 288: ...ControlCurrentED Register R W Reset Value 00000000h 31 4 ControlCurrentED Pointer to the current Control List ED 3 0 Reserved Read Write 0s Offset 28h 2Bh HcBulkHeadED Register R W Reset Value 0000000...

Page 289: ...t Value 01000003h 31 24 PowerOnToPowerGoodTime This field value is represented as the number of 2 ms intervals ensuring that the power switching is effective within 2 ms Only bits 25 24 are implemente...

Page 290: ...ion Offset 50h 53h HcRhStatus Register R W Reset Value 00000000h 31 ClearRemoteWakeupEnable Write Only Writing a 1 to this bit clears DeviceRemoteWakeupEnable Writing a 0 has no effect 30 18 Reserved...

Page 291: ...edDeviceAttached This bit defines the speed and bud idle of the attached device It is only valid when CurrentConnectStatus is set 0 Full Speed device 1 Low Speed device Write ClearPortPower Writing a...

Page 292: ...ates that the port has been disabled due to a hardware event cleared PortEna bleStatus 0 Port has not been disabled 1 PortEnableStatus has been cleared 16 ConnectStatusChange This bit indicates a conn...

Page 293: ...31 21 Reserved Read Write 0s 20 PortResetStatusChange This bit indicates that the port reset signal has completed 0 Port reset is not complete 1 Port reset is complete 19 PortOverCurrentIndicatorChan...

Page 294: ...rentProtection is cleared and OverCurrentProtectionMode is set 0 No over current condition 1 Over current condition Write ClearPortSuspend Writing a 1 initiates the selective resume sequence for the p...

Page 295: ...rt various status information Offset 104h 107h HceInput Register R W Reset Value 000000xxh 31 8 Reserved Read Write 0s 7 0 InputData This register holds data written to I O ports 60h and 64h Note This...

Page 296: ...able 6 43 DMA Channel Control Registers Bit Description I O Port 000h DMA Channel 0 Address Register R W Written as two successive bytes byte 0 1 I O Port 001h DMA Channel 0 Transfer Count Register R...

Page 297: ...ate write 1 Extended write 4 Priority Mode 0 Fixed 1 Rotating 3 Timing Mode 0 Normal 1 Compressed 2 Channels 3 0 0 Disable 1 Enable 1 0 Reserved Must be set to 0 I O Port 009h Software DMA Request Reg...

Page 298: ...h DMA Master Clear Command Channels 3 0 W I O Port 00Eh DMA Clear Mask Register Command Channels 3 0 W I O Port 00Fh DMA Write Mask Register Command Channels 3 0 W I O Port 0C0h DMA Channel 4 Address...

Page 299: ...7 Terminal Count Indicates if TC was reached 0 No 1 Yes 2 Channel 6 Terminal Count Indicates if TC was reached 0 No 1 Yes 1 Channel 5 Terminal Count Indicates if TC was reached 0 No 1 Yes 0 Undefined...

Page 300: ...er Channels 7 4 WO Note Channels 5 6 and 7 are not supported 7 6 Transfer Mode 00 Demand 01 Single 10 Block 11 Cascade 5 Address Direction 0 Increment 1 Decrement 4 Auto initialize 0 Disabled 1 Enable...

Page 301: ...Port 08Ah DMA Channel 7 Low Page Register R W Not supported I O Port 08Bh DMA Channel 5 Low Page Register R W Not supported I O Port 08Fh ISA Refresh Low Page Register R W Refresh address I O Port 48...

Page 302: ...ad Write Mode 00 Counter latch command 01 R W LSB only 10 R W MSB only 11 R W LSB followed by MSB 3 1 Current Counter Mode 0 5 0 BCD Mode 0 Binary 1 BCD Binary Coded Decimal I O Port 041h Write PIT Ti...

Page 303: ...imal I O Port 043h R W PIT Mode Control Word Register Notes 1 If bits 7 6 11 Register functions as Read Status Command and Bit 5 Latch Count Bit 4 Latch Status Bit 3 Select Counter 2 Bit 2 Select Coun...

Page 304: ...for interrupt controller 2 0 Reserved Must be set to 0 I O Port 021h 0A1h Master Slave PIC ICW3 after ICW2 is written WO Master PIC ICW3 7 0 Cascade IRQ Must be 04h Slave PIC ICW3 7 0 Slave ID Must be...

Page 305: ...Special Mask Mode 00 No operation 01 No operation 10 Reset Special Mask Mode 11 Set Special Mask Mode 4 Reserved Must be set to 0 3 Reserved Must be set to 1 2 Poll Command 0 Disable 1 Enable 1 0 Regi...

Page 306: ...rvice Register 7 IRQ7 IRQ15 In Service 0 No 1 Yes 6 IRQ6 IRQ14 In Service 0 No 1 Yes 5 IRQ5 IRQ13 In Service 0 No 1 Yes 4 IRQ4 IRQ12 In Service 0 No 1 Yes 3 IRQ3 IRQ11 In Service 0 No 1 Yes 2 IRQ2 IRQ...

Page 307: ...driven low by an I O device to report an error Note that NMI is under SMI control 1 Ignores the IOCHK input signal and does not generate NMI 2 PERR SERR Enable Generate an NMI if PERR SERR is driven...

Page 308: ...O Port 0F0h 0F1h Coprocessor Error Register W Reset Value F0h A write to either port when the internal FERR signal is asserted causes the Core Logic Module to assert internal IGNNE IGNNE remains asse...

Page 309: ...Select Selects PIC IRQ15 sensitivity configuration 0 Edge 1 Level 6 IRQ14 Edge or Level Sensitive Select Selects PIC IRQ14 sensitivity configuration 0 Edge 1 Level 5 Reserved Must be set to 0 4 IRQ12...

Page 310: ...310 AMD Geode SC1200 SC1201 Processor Data Book Core Logic Module ISA Legacy Register Space 32579B...

Page 311: ...tal filtering and downscaling Supports 4 2 2 4 2 0 YUV formats and RGB 5 6 5 format Graphics Video Overlay and Blending Overlay of video up to 16 bpp Supports chroma key and color key for both graphic...

Page 312: ...eo Processor module includes the following functions Video Input Port CCIR 656 decoder Capture Video VBI modes Direct Video VBI modes Video Formatter Asynchronous video interface Horizontal Vertical s...

Page 313: ...ame buffer The VIP block supports the CCIR 656 data protocol The CCIR 656 protocol supports TV data NTSC or PAL and defines the format for active video data and vertical blanking interval VBI data Con...

Page 314: ...gical Lines 2 3 Scan Lines 2 3 VSYNC Start VBI_Total_Count_Odd VBI_Line_Offset_Odd Not normally User Data Nominal VBI Lines Not normally User Data Not normally User Data VSYNC End Vertical Retrace Log...

Page 315: ...decoder s data A 2048 byte FIFO buffers Video data and a 128 byte FIFO buffers VBI data The FIFOs are also used to provide clock domain changes The VIP inter face clock nominally 27 MHz is the input...

Page 316: ...mode operation is very similar to Direct Video mode and is also on by default The VBI mux control is located at F4BAR0 Memory Offset 400h 2 Specific VBI lines may be blocked or nulled before they are...

Page 317: ...ry Offset 24h Video Data Even Base Address F4BAR2 Memory Offset 28h Video Data Pitch The Video Data Even Base Address must be sepa rated from the Video Data Odd Base Address by at least the field data...

Page 318: ...Offset 28h Video Data Pitch The Video Data Even Base Address must be sepa rated from the Video Data Odd Base Address by one horizontal line The Video Data Pitch register must be programmed to one hor...

Page 319: ...then this option is not possible because the video frame buffer can be used for sending video or VBI but not simultaneously The registers F4BAR2 Memory Offset 40h 44h and 48h tell the bus master the d...

Page 320: ...6 5 For this format each pixel is described as a 16 bit value Bits 15 11 Red Bits 10 5 Green Bits 4 0 Blue YUV 4 2 0 This format is not supported by the GX1 mod ule The Horizontal Downscaler in the V...

Page 321: ...ntaining Aspect Ratio The main purpose of the horizontal downscaler is to main tain the aspect ratio of graphics data displayed on a TV which was originally generated for CRT display NTSC has an aspec...

Page 322: ...l Upscalers After the video data has been buffered the upscaling algo rithm can be applied The Video Processor employs a Digi tal Differential Analyzer style DDA algorithm for both horizontal and vert...

Page 323: ...red and the RGB to YUV CSC is used on the graphics data when YUV blending is desired If Gamma Correction see Section 7 2 3 2 on the video data is desired it must be done in the color space of the inpu...

Page 324: ...be used to support simultaneous operation 1 0 0 0 0 0 Input RGB Progressive Video Mixing RGB Flicker Filter TV Display Supported but not recommended Non optimal operation of the flicker filter CRT TFT...

Page 325: ...VOUT block RGB graphics data or mixed blended graphics video data is passed through this CSC to obtain 24 bit YUV data using the following CCIR 601 1 recommended formula Y 0 257R 0 504G 0 098B 16 U 0...

Page 326: ...dware cursor or a software cursor When using the hardware cursor the displayed colors of the hard ware cursor must be the cursor color keys see Section 5 5 3 Hardware Cursor in the AMD Geode GX1 Pro c...

Page 327: ...Data Match Normal Color Key Video Data Match Normal Color Key Mixer Output x x x Yes x x Cursor Color x Not in Video Window x No x x Graphics Data Graphics Color Key COLOR_ CHROMA_SEL 0 Not in an Alp...

Page 328: ...Yes Yes Replace the value with the color register value Yes Start Notes 1 Alpha window should not be placed outside of the video window 2 Graphics inside Video is enabled via bit GFX_INS_VIDEO in the...

Page 329: ...ing must be the Mixer Blender block s mode see Sec tion 7 2 3 Mixer Blender Block on page 323 In this mode the Mixer Blender block supports the flicker filter process see Figure 7 10 on page 323 Then...

Page 330: ...ral Configuration Block see Section 4 2 Pin Multi plexing Interrupt Selection and Base Address Registers on page 72 7 2 4 4 TV Encoder Timing Generator The timing generator generates all the necessary...

Page 331: ...is 80 MHz Support for a TFT panel requires power sequencing and an 18 bit 6 bit RGB digital output The relevant digital output signals are available from the SC1200 SC1201 processor TFT output signals...

Page 332: ...d an integrated oscillator FOUT is calculated from FOUT m 1 n 1 x FREF The integrated PLL can generate any frequency by writing into the CRT m and CRT n bit fields FBAR0 Memory Off set 2Ch Additionall...

Page 333: ...ess Register 0 F4BAR0 Sets the base address for the memory mapped Video Configuration Registers within the Video Processor Refer to Table 7 9 on page 338 for programming infor mation regarding the reg...

Page 334: ...W Alpha Window 2 Y Position Register 00000000h Page 347 78h 7Bh 32 R W Alpha Window 2 Color Register 00000000h Page 348 7Ch 7Fh 32 R W Alpha Window 2 Control Register 00000000h Page 348 80h 83h 32 R...

Page 335: ...32 R W WSS Data Register 00000000h Page 357 C28h C2Bh 32 R W Closed Captioning Control Register 00000000h Page 357 C2Ch C2Fh 32 R W DAC Control Register 00000020h Page 358 C50h C53h 32 R W VBI Scaler...

Page 336: ...h Index 0Ch PCI Cache Line Size Register RO Reset Value 00h Index 0Dh PCI Latency Timer Register RO Reset Value 00h Index 0Eh PCI Header Type RO Reset Value 00h Index 0Fh PCI BIST Register RO Reset Va...

Page 337: ...errupt Pin Register R W Reset Value 03h This register selects which interrupt pin the device uses VIP uses INTC after reset INTA INTB or INTD can be selected by writing 1 2 or 4 respectively Index 3Eh...

Page 338: ...the left edge of the active display It represents the DWORD address of the source pixel which is to be displayed first For an unclipped window this value should be 0 For 4 2 0 format set bits 17 16 t...

Page 339: ...hether the graphics or video data goes to the Gamma Correction RAM GAMMA_EN F4BAR0 Memory Offset 28h 0 must be enabled for the selected data source to pass through the Gamma Correction RAM 0 Graphics...

Page 340: ...register is programmed relative to CRT horizontal sync input not physical screen position Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller Timing registers GX_B...

Page 341: ..._SCL 8192 but the formula above fits a given source number of pixels into a destination win dow size Offset 14h 17h Video Color Key Register R W Reset Value 00000000h Provides the video color key The...

Page 342: ...period This effect should go unnoticed during normal operation 7 0 Reserved Offset 24h 27h Reserved Offset 28h 2Bh Miscellaneous Register R W Reset Value 00001400h Configuration and control register...

Page 343: ...S Downscale Type Select 0 Type A Downscale formula is 1 m 1 m pixels are dropped 1 pixel is kept 1 Type B Downscale formula is m m 1 m pixels are kept 1 pixel is dropped 5 Reserved 4 1 DFS Downscale F...

Page 344: ...can then be reset to initialize the SIG_VALUE as an essential preparation for the next round of CRC check Offset 48h 4Bh Device and Revision Identification RO Reset Value 0000xxxxh 31 16 Reserved 15...

Page 345: ...ODE Video Blending Mode Allows selection of the type of video i e interlaced or progressive used for blending 0 Progressive video used for blending 1 Interlaced video used for blending Note Mixing and...

Page 346: ...even selects this color to be used Offset 60h 63h Alpha Window 1 X Position Register R W Reset Value 00000000h Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller...

Page 347: ...to be used for this window Offset 70h 73h Alpha Window 2 X Position Register R W Reset Value 00000000h Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller Timing...

Page 348: ...value to be used for this window Offset 80h 83h Alpha Window 3 X Position Register R W Reset Value 00000000h Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller T...

Page 349: ...value that is added to the alpha value for each frame The MSB bit 15 indicates the sign i e increment or decrement When this value reaches either the maximum or the minimum alpha value 255 or 0 it ke...

Page 350: ...active at all times regardless of the source of video input Offset 404h 407h Reserved Reset Value 00000000h Offset 408h 40Bh Video Processor Test Mode Register R W Reset Value 00000000h 31 0 Reserved...

Page 351: ...ndicates CGENTO0 F4BAR0 Memory Offset 43Ch 15 0 has expired This bit can be reset by writing 1 to it 22 EVEN_TO Even Field Time Out Indicates CGENTO1 F4BAR0 Memory Offset 43Ch 31 16 has expired This b...

Page 352: ...uous GenLock Timeout Offset 800h 803h Horizontal Timing Register R W Reset Value 00000000h This register is updated at each occurrence of HSYNC 31 28 Reserved 27 16 H_DISP_START Horizontal Display Sta...

Page 353: ...ker filter when interlaced blending is used 10 Flicker filter disabled 11 Reserved 28 H_REF_SEL Horizontal Reference Select Selects reference for the horizontal display position 0 HSYNC generated in t...

Page 354: ...nters in the video timing generator are disabled the sync signals are disabled and the blank signals are asserted 0 Disable 1 Enable 30 IPS Invert PAL Switch When set inverts the sense of the PAL Swit...

Page 355: ...lf line counter is reset the line half indicator toggles In PAL mode there are 1728 27 MHz clock cycles per line In this mode the half line counter counts 0 to 863 To set the hor izontal phase to a va...

Page 356: ...cal start position of the top field relative to the start of VSYNC line 1 for PAL line 4 for NTSC For 480 line NTSC this field is set to 18 12h For 576 line PAL this field is set to 22 16h 15 10 Reser...

Page 357: ...F4BAR0 Memory Offset C28h 12 8 The data is modulated on to the specified line in the top and or bottom field according to the setting of bits 14 13 in the Closed Captioning Control register The bits a...

Page 358: ...11 Select external voltage reference 2 0 TRIM The value in this field is used to adjust the internal voltage reference Offset C50h C53h VBI Scaler Register Reset Value 00000004h 31 17 Reserved 16 VBI_...

Page 359: ...ide 1 enabled 18 VBI Configuration Override When this bit is enabled bits 21 19 override the setup specified in bits 17 and 16 0 Disable 1 Enable 17 VBI Data Task Specifies the CCIR 656 video stream t...

Page 360: ...ure at beginning of next field Offset 08h 0Bh Video Interface Status Register R W Reset Value xxxxxxxxh 31 25 Reserved Read Only 24 Current Field Read Only 0 Even field is being processed 1 Odd field...

Page 361: ...beginning of the next field The value in this register is 16 byte aligned Note This register is double buffered When a new value is written to this register the new value is placed in a special pendin...

Page 362: ...here VBI data for odd fields is stored in graphics memory Bits 3 0 are always 0 and define the required address space Offset 44h 47h VBI Data Even Base Register R W Reset Value 00000000h This register...

Page 363: ...Support The TAP supports the following IEEE optional instructions IDCODE Presents the contents of the Device Identification register in serial format CLAMP Ensures that the Bypass register is connect...

Page 364: ...364 AMD Geode SC1200 SC1201 Processor Data Book Debugging and Monitoring 32579B...

Page 365: ...se indicated in the following table may cause permanent damage to the SC1200 SC1201 proces sor reduce device reliability and result in premature failure even when there is no immediately apparent sign...

Page 366: ...the boundary between voltage domains Table 9 3 Operating Conditions Symbol Note 1 Note 1 For VIH Input High Voltage VIL Input Low Voltage IOH Output High Current and IOL Output Low Current op erating...

Page 367: ...ent to the ACPI specification s S1 state 9 1 5 2 Definition and Measurement Techniques of Current Parameters These parameters describe the current while the SC1200 SC1201 processor is in the On state...

Page 368: ...ystem Conditions VCORE Note 1 VIO Note 1 DCLK Frequency SDRAM Frequency Typical Average Nominal Nominal 50 MHz Note 2 Nominal Absolute Maximum Max Max 135 MHz Note 3 Max Note 1 See Table 9 3 on page 3...

Page 369: ...e 3 IBAT BAT Current VBAT 3 0 Nominal CPU state Off 7 15 A TC 25 C Note 4 IBAT BAT Current VBAT 3 0 Nominal CPU state Off 7 50 A TC 25 C Note 1 fCLK ratings refer to internal clock frequency Note 2 Al...

Page 370: ...TFT_PRSNT P29 PD 100K LPC_ROM D6 PD 100K FPCI_MON A4 PD 100K DID 1 0 C6 C5 PD 100K ACCESS bus Note 2 AB1C N31 PU 22 5K AB1D N30 PU 22 5K AB2C N29 PU 22 5K AB2D M29 PU 22 5K Parallel Port AFD DSTRB D2...

Page 371: ...Strap ball min VIH is 0 6VIO with weak pull down Section 9 2 4 INT Input TTL compatible Section 9 2 5 INTS Input TTL compatible with Schmitt Trigger type 200 mV Section 9 2 6 INTS1 Input with Schmitt...

Page 372: ...ote 1 V VIL Input Low Voltage 0 5 Note 1 0 8 V IIL Input Leakage Current 5 A VIN VSB 36 A VIN VSS VHIS Input Hysteresis 250 mV Note 1 Note 1 Not 100 tested Symbol Parameter Min Max Unit Comments VIH I...

Page 373: ...Unit Comments VIH Input High Voltage 2 0 VIO 0 3 Note 1 V VIL Input Low Voltage 0 5 Note 1 0 8 V IIL Input Leakage Current 10 A VIN VIO 10 A VIN VSS Note 1 Not 100 tested Symbol Parameter Min Max Unit...

Page 374: ...nt 10 A VIN VIO 10 A VIN VSS VDI Differential Input Sensitivity 0 2 V D D and Figure 9 1 VCM Differential Common Mode Range 0 8 2 5 V Includes VDI Range VSE Single Ended Receiver Threshold 0 8 2 0 V N...

Page 375: ...er Min Max Unit Comments VOL Output Low Voltage 0 1VIO V lOL 1500 A Symbol Parameter Min Max Unit Comments VOH Output High Voltage 2 4 V lOH p mA VOL Output Low Voltage 0 4 V lOL n mA Symbol Parameter...

Page 376: ...conform to these default levels All AC tests are at VIO 3 14V to 3 46V 3 3V nominal TC 0 oC to 85 oC CL 50 pF unless otherwise specified Figure 9 2 General Drive level and Measurement Points Table 9 1...

Page 377: ...mpling window during which a synchronous input signal must be stable to ensure correct operation Figure 9 3 Memory Controller Drive Level and Measurement Points SDCLK_OUT VOH VREF VREF VREF C Valid Ou...

Page 378: ...between VOLD VOHD 2 ns t9 SDCLK_IN fall rise time between VILD VIHD 2 ns t10 SDCLK 3 0 SDCLK_OUT high time 3 0 t11 SDCLK 3 0 SDCLK_OUT low time 2 5 Note 1 Control output includes all the following si...

Page 379: ...re 9 4 Memory Controller Output Valid Timing Diagram Figure 9 5 Read Data In Setup and Hold Timing Diagram SDCLK 3 0 Control Output MA 12 0 BA 1 0 MD 63 0 t1 t2 t3 t6 t7 t7 VREF VOHD VOLD VREF t10 t11...

Page 380: ...g Parameters Symbol Parameter Min Max Unit Comments tVP_C VPCKIN cycle time 18 ns tVP_S Video Port input setup time before VPCKIN rising edge 6 ns tVP_H Video Port input hold time after VPCKIN rising...

Page 381: ...bol Parameter Min Max Unit Comments tVP_C VOPCK cycle time 36 38 ns tVP_V Video Port output data valid after VOPCK rising edge 15 ns tVP_H Video Port output data hold after VOPCK rising edge 0 ns tVPC...

Page 382: ...dard ACCESS bus timing and are controlled by software Figure 9 8 TFT Timing Diagram Table 9 15 TFT Timing Parameters Symbol Parameter Min Max Unit Comments tOV TFTD 17 0 TFTDE valid time after TFTDCK...

Page 383: ...T Max output capacitance 15 pF PSRR Power supply rejection ratio 3 5 At 0 to 1 MHz Note 6 Note 1 Black level Blank level 0 mA 0V Note 2 The maximum difference between the ideal straight conversion lin...

Page 384: ...al input 3FFh INL Integral linearity error 1 5 LSB Note 1 DNL Differential linearity error 1 5 LSB Note 2 TVREF Internal reference voltage 1 17 1 29 V Typically 1 235V Gain Error Gain Error 5 DDM DAC...

Page 385: ...C AB2C falling edge tSCLhighi AB1C AB2C high time 16 tCLK After AB1C AB2C rising edge tSDAfi AB1D AB2D fall time 300 ns tSDAri AB1D AB2D rise time 1 s tSDAhi AB1D AB2D hold time 0 After AB1C AB2C fall...

Page 386: ...vo AB1D AB2D valid time 7 tCLK tRD After AB1C AB2C falling edge Note 1 K is determined by bits 7 1 of the ACBCTL2 register LDN 05h 06h Offset 05h Note 2 tSCLhigho value depends on the signal capacitan...

Page 387: ...2579B Figure 9 11 ACB Start Condition TIming Diagram Figure 9 12 ACB Data Bit Timing Diagram tCSTRsi tDHCsi Start Condition tCSTRhi AB1D AB1C tCSTRho tCSTRso tDHCso AB2D AB2C tSCLhigho tSCLlowo tSDAho...

Page 388: ...0 6VIO VOUT 0 1VIO Equation B Figure 9 14 0 18VIO VOUT 0 Test point Note 2 38VIO mA VOUT 0 18VIO ICL Low clamp current 25 VIN 1 0 015 mA 3 VIN 1 ICH High clamp current 25 VIN VIO 1 0 015 mA VIO 4 VIN...

Page 389: ...Down Test Point VIO 0 9 VIO DC Drive Point AC Drive Point 0 3 VIO 0 6 VIO 0 1 AC Drive Point DC Drive Point Test Point VIO Equation A for VIO VOUT 0 7VIO IOL 256 VIO VOUT VIO VOUT for 0V VOUT 0 18VIO...

Page 390: ...lew Rate 50 mV ns Note 4 Note 1 Clock frequency is between nominal DC and 33 MHz Device operational parameters at frequencies under 16 MHz are not 100 tested The clock can only be stopped in a low sta...

Page 391: ...able 1 ms Note 3 Note 5 tRST CLK PCIRST active time after PCICLK stable 100 s Note 3 Note 5 tRST OFF PCIRST active to output float delay 40 ns Note 3 Note 5 Note 6 Note 1 See the timing measurement co...

Page 392: ...Note 1 VTL 0 2 VIO V Note 1 VTEST 0 4 VIO V VSTEP rising edge 0 285 VIO V VSTEP falling edge 0 615 VIO V VMAX 0 4 VIO V Note 2 Input signal edge rate 1 V ns Note 1 The input test is performed with 0 1...

Page 393: ...nt Conditions Figure 9 19 PCI Reset Timing VTEST VTEST Input Valid tSU tH VTEST VMAX VTH VTL PCICLK Input VTH VTL 100 ms typ tRST tRST CLK tRST OFF TRI_STATE PCI Signals PCIRST PCICLK POWER POR tFAIL...

Page 394: ...FE to RE 8 M I O 160 9 20 Zero wait state tRCU1 MEMR DOCR RD TRDE inactive pulse width 16 M 103 9 20 tRCU2 MEMR DOCR RD TRDE inactive pulse width 8 M 163 9 20 tRCU3 IOR RD TRDE inactive pulse width 8...

Page 395: ...16 M I O 0 9 20 tHZ Read data floating after MEMR DOCR IOR inactive 8 16 M I O 41 9 20 tAW1 A 23 0 BHE valid before MEMW DOCW active 16 M 34 9 21 tAW2 A 23 0 BHE valid before IOW active 16 I O 100 9...

Page 396: ...0 Sub ISA Read Operation Timing Diagram tRDx tARx Valid Valid Valid Data tRCUx tRA tRVDS tRDH tHZ A 23 0 BHE D 15 0 tRDYAx tRDYH MEMW DOCW ROMCS DOCCS IOW WR IOCS 1 0 Read tIOCSA tIOCSH tWDAR D 15 0 W...

Page 397: ...Figure 9 21 Sub ISA Write Operation Timing Diagram tWRx tAWx Valid Valid Valid Data tWCUx tWA tDH A 23 0 BHE TRDE D 15 0 IOCHRDY tRDYAx tRDYH DOCCS ROMCS tIOCSH IOCS 1 0 tDF tDVx tIOCSA IOW WR MEMW DO...

Page 398: ...Q Symbol Parameter Min Max Unit Comments tVAL Output Valid delay 0 17 ns After PCICLK rising edge tON Float to Active delay 2 ns After PCICLK rising edge tOFF Active to Float delay 28 ns After PCICLK...

Page 399: ...igure 9 24 IDE Reset Timing Diagram Table 9 26 IDE General Timing Parameters Symbol Parameter Min Max Unit Comments tIDE_FALL IDE signals fall time from 0 9VIO to 0 1VIO 5 ns CL 40 pF tIDE_RISE IDE si...

Page 400: ...x 5 5 5 5 5 ns Note 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recov ery time or command inactive time The actual cycle time equals the s...

Page 401: ...ter tA from the assertion of IDE_IOR 0 1 or IDE_IOW 0 1 3 Device never negates IDE_IORDY 0 1 Device keeps IDE_IORDY 0 1 released and no wait is generated 4 Device negates IDE_IORDY 0 1 before tA but c...

Page 402: ...5 ns Note 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recov ery time or command inactive time The actual cycle time equals the sum of the...

Page 403: ...nded is made by the host after tA from the assertion of IDE_IOR 0 1 or IDE_IOW 0 1 3 Device never negates IDE_IORDY 0 1 Devices keep IDE_IORDY 0 1 released and no wait is generated 4 Device negates ID...

Page 404: ...ated pulse width min 215 50 25 ns tLR IDE_IOR 0 1 to IDE_DREQ 0 1 delay max 120 40 35 ns tLW IDE_IOW 0 1 to IDE_DREQ0 1 delay max 40 40 35 ns tM IDE_CS 0 1 valid to IDE_IOR 0 1 IDE_IOW 0 1 min 50 30 2...

Page 405: ...0 IDE_IOW0 Notes 1 For Multiword DMA transfers the Device may negate IDE_DREQ 0 1 within the tL specified time once IDE_DACK 0 1 is asserted and reassert it again at a later time to resume the DMA ope...

Page 406: ...ated 10 10 10 ns tZAH Minimum delay time required for output driv ers to assert or negate from released state 20 20 20 ns tZAD 0 0 0 ns tENV Envelope time from IDE_DACK 0 1 to IDE_IOW 0 1 STOP 0 1 and...

Page 407: ...ements are taken at the connector of the sender Figure 9 28 Initiating an UltraDMA Data in Burst Timing Diagram tUI tACK tENV tFS tFS tZAD tACK tZIORDY tAZ tACK tDVS tDVH tENV tZAD IDE_DATA 15 0 IDE_A...

Page 408: ...CYC IDE_DATA 15 0 at device IDE_DATA 15 0 at host IDE_IRDY0 DSTROBE0 at device IDE_IRDY0 DSTROBE0 at host Note IDE_DATA 15 0 and IDE_IRDY 0 1 DSTROBE 0 1 signals are shown at both the host and the dev...

Page 409: ...RFS tSR IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Notes 1 The host can assert IDE_IOW 0 1 STOP 0 1 to request termination of the UltraDMA bur...

Page 410: ...CS 0 1 IDE_ADDR 2 0 CR tACK tDVH tDVS tZAH tAZ tSS tLI tACK tIORDZ tACK tMLI tLI tLI IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The defin...

Page 411: ...1 IDE_ADDR 2 0 CR tACK tDVH tDVS tACK tIORDYZ tACK tMLI tLI tRP tMLI tLI tRFS tAZ tZAH IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The de...

Page 412: ...ice IDE_CS 0 1 IDE_ADDR 2 0 tUI tACK tENV tLI tUI tZIORDY tACK tDVS tDVH tACK IDE_DACK0 host IDE_DREQ0 device IDE_IOW0 STOP0 host IDE_IORDY0 DDMARDY0 device IDE_IOR0 HSTROBE0 host Note The definitions...

Page 413: ...2CYC IDE_DATA 15 0 at host IDE_DATA 15 0 at device IDE_IOR0 HSTROBE0 at host IDE_IOR0 HSTROBE0 at device Note IDE_DATA 15 0 and IDE_IOR 0 1 HSTROBE 0 1 signals are shown at both the device and the hos...

Page 414: ...tRFS tSR IDE_IOR0 HSTROBE0 host IDE_DACK0 host IDE_DREQ0 device IDE_IOW0 STOP0 host IDE_IORDY0 DDMARDY0 device Notes 1 The device can de assert IDE_DREQ 0 1 to request termination of the UltraDMA burs...

Page 415: ...E_CS 0 1 IDE_ADDR 2 0 CR tLI tMLI tACK tLI tSS tLI tACK tDVH tDVS tACK tIORDYZ IDE_IOR0 HSTROBE0 host IDE_IORDY0 DDMARDY0 device IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The definition...

Page 416: ...CS 0 1 IDE_ADDR 2 0 CR tACK tDVH tDVS tRFS tACK tIORDZ tACK tMLI tLI tRP tMLI tLI IDE_IOR0 HSTROBE0 host IDE_IORDY0 DDMARDY0 device IDE_DREQ0 device IDE_DACK0 host IDE_IOW0 STOP0 host Note The definit...

Page 417: ...P width 160 175 ns 9 39 Note 4 Note 5 tUSB_DE1 Differential to EOP transition skew 2 5 ns 9 40 Note 4 Note 5 tUSB_RJ11 Receiver data jitter tolerance for con secutive transition 18 5 18 5 ns 9 41 Note...

Page 418: ...ownstream Note 4 tUSB_RJU22 Receiver data jitter tolerance for paired transactions 45 45 ns 9 41 Function downstream Note 4 Low Speed Receiver EOP Width Note 5 tUSB_RE21 Must reject as EOP 330 ns 9 39...

Page 419: ...2 90 90 10 10 Differential Data Lines CL CL Full Speed 4 to 20 ns at CL 50 pF Low Speed 75 ns at CL 50 pF 300 ns at CL 350 pF tperiod_F Paired Transitions Consecutive Transitions Differential Data Lin...

Page 420: ...L Differential Data to SE0 Skew N tperiod_F tUSB_DE1 N tperiod_L tUSB_DE2 tUSB_SE1 tUSB_SE2 tUSB_RE11 tUSB_RE12 tUSB_RE21 tUSB_RE22 Source Receiver tperiod_F Paired Transitions Consecutive Transitions...

Page 421: ...nsmitter 2 0 Receiver tSJT SIR leading edge jitter of nominal bit duration 2 5 Transmitter 6 5 Receiver Note 1 tBTN is the nominal bit time in UART Sharp IR SIR and Consumer Remote Control modes It is...

Page 422: ...ta rate tolerance 0 1 tMJT MIR receiver edge jitter of nominal bit duration 2 9 tFPW FIR signal pulse width 120 130 ns Transmitter 90 160 ns Receiver tFDPW FIR signal double pulse width 245 255 ns Tra...

Page 423: ...el Port Typical Data Exchange Timing Diagram Table 9 34 Standard Parallel Port Timing Parameters Symbol Parameter Min Typ Max Unit Comments tPDH Port data hold 500 ns Note 1 tPDS Port data setup 500 n...

Page 424: ...m WAIT low 45 x ns tWW19ia WRITE inactive from WAIT low 45 x ns tWST19a DSTRB or ASTRB active from WAIT low 65 x ns tWEST DSTRB or ASTRB active after WRITE active 10 x x ns tWPDH PD 7 0 hold after WRI...

Page 425: ...orward Mode Timing Parameters Symbol Parameter Min Max Unit Comments tECDSF Data setup before STB active 0 ns tECDHF Data hold after BUSY inactive 0 ns tECLHF BUSY active after STB active 75 ns tECHHF...

Page 426: ...rameters Symbol Parameter Min Max Unit Comments tECDSR Data setup before ACK active 0 ns tECDHR Data hold after AFD active 0 ns tECLHR AFD inactive after ACK active 75 ns tECHHR ACK inactive after AFD...

Page 427: ...g Parameters Symbol Parameter Min Typ Max Unit Comments tRST_LOW AC97_RST active low pulse width 1 0 s tRST2CLK AC97_RST inactive to BIT_CLK startup delay 162 8 ns AC97_RST BIT_CLK tRST_LOW tRST2CLK T...

Page 428: ...low pulse width 32 56 40 7 48 84 ns Note 1 FSYNC SYNC frequency 48 0 KHz tSYNC_PD SYNC period 20 8 s tSYNC_H SYNC high pulse width 1 3 s tSYNC_L SYNC low pulse width 19 5 s FAC97_CLK AC97_CLK frequen...

Page 429: ...ng edge of BIT_CLK 15 0 ns tAC97_H Hold from falling edge of BIT_CLK 10 0 ns tAC97_OV SDATA_OUT or SYNC valid after rising edge of BIT_CLK 15 ns tAC97_OH SDATA_OUT or SYNC hold time after falling edge...

Page 430: ...BIT_CLK rise time 2 6 ns tfallCLK BIT_CLK fall time 2 6 ns triseSYNC SYNC rise time 2 6 ns CL 50 pF tfallSYNC SYNC fall time 2 6 ns CL 50 pF triseDIN SDATA_IN rise time 2 6 ns tfallDIN SDATA_IN fall t...

Page 431: ...B Figure 9 53 AC97 Low Power Mode Timing Diagram Table 9 43 AC97 Low Power Mode Timing Parameters Symbol Parameter Min Typ Max Unit Comments ts2_pdown End of Slot 2 to BIT_CLK SDATA_IN low 1 0 s SYNC...

Page 432: ...ing Diagram Table 9 44 PWRBTN Timing Parameters Symbol Parameter Min Max Unit Comments tPBTNP PWRBTN pulse width 16 ms Note 1 tPBTNE Delay from PWRBTN events to ONCTL 14 16 ms Note 1 Not 100 tested PW...

Page 433: ...B or VSBL applied whichever is applied last 0 1 s PWRBTN is an input and must be powered by VSB t3 PWRBTN active pulse width 16 4000 ms If PWRBTN max is exceeded ONCTL will go inactive t4 ONCTL inacti...

Page 434: ...ee Section 6 4 1 1 GPIO Sup port Registers on page 224 GPIO63 must be pulsed low for at least 16 ms and not more than 4 sec Asserting POR has no effect on ACPI If POR is asserted and ACPI was active p...

Page 435: ...frequency 25 MHz t1 TCK period 40 ns t2 TCK high time 10 ns t3 TCK low time 10 ns t4 TCK rise time 4 ns t5 TCK fall time 4 ns t6 TDO valid delay 3 25 ns t7 Non test outputs valid delay 3 25 ns 50 pF...

Page 436: ...436 AMD Geode SC1200 SC1201 Processor Data Book Electrical Specifications 32579B Figure 9 59 JTAG Test Timing Diagram TCK t8 Input Output TDO TDI t11 t13 t9 t7 t6 t12 t10 TMS Signals Signals...

Page 437: ...active thermal management via Sus pend Modulation of the GX1 module is employed A maximum junction temperature is not specified since a maximum case temperature is Therefore the following equation can...

Page 438: ...bove ambi ent in C This method is necessary because ambient and case temperatures fluctuate constantly during normal oper ation of the system The system designer must be careful to choose the proper h...

Page 439: ...Data Book 439 Package Specifications 32579B 10 2 Physical Dimensions The figures in this section provide the mechanical package outlines for the BGU481 481 Terminal Ball Grid Array Cavity Up package F...

Page 440: ...440 AMD Geode SC1200 SC1201 Processor Data Book Package Specifications 32579B Figure 10 3 BGU481 Package Bottom View...

Page 441: ...f Macrovision Corporation Ordering Part Number AMD OPN 1 1 The F suffix denotes the Pb free lead free package See Section 10 0 on page 437 for the BGU481 481 terminal Ball Grid Array Cavity Up package...

Page 442: ...81 data Several other cor rections changes were made to specific sections See revision 4 0 for a list of all changes 4 1 June 2002 Release for posting on external web site Changes made to the Architec...

Page 443: ...One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 749 4000 or 800 538 8450 TWX 910 339 9280 TELEX 34 6306 www amd com...

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