Interrupt Control Unit
7-34
7.4.8
Interrupt Mask Register (IMASK, Offset 28h)
(Slave Mode)
The format of the Interrupt Mask register is shown in Figure 7-24. The Interrupt Mask register
is a read/write register. Programming a bit in the Interrupt Mask register has the effect of
programming the MSK bit in the associated control register.
Figure 7-24
Interrupt Mask Register (IMASK, offset 28h)
The IMASK register is set to 003Dh on reset.
Bits 15–6: Reserved
Bits 5–4: Timer 2/Timer 1 Interrupt Mask (TMR2–TMR1)—These bits indicate the state
of the mask bit of the Timer Interrupt Control register and when set to a 1, indicate which
source has its interrupt requests masked.
Bits 3–2: DMA Channel Interrupt Mask (D1–D0)—These bits indicate the state of the
mask bits of the corresponding DMA control register.
Bit 1: Reserved
Bit 0: Timer 0 Interrupt Mask (TMR0)—This bit indicates the state of the mask bit of the
Timer Interrupt Control register and when set to a 1, indicates Timer 0 has its interrupt
request masked.
15
7
0
Reserved
D0
D1
TMR1
TMR2
Res
TMR0
Summary of Contents for AM186EM
Page 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Page 4: ...iv...
Page 12: ...Table of Contents xii...
Page 62: ...Peripheral Control Block 4 10...
Page 76: ...Chip Select Unit 5 14...
Page 122: ...Timer Control Unit 8 8...
Page 136: ...DMA Controller 9 14...
Page 144: ...Asynchronous Serial Port 10 8...
Page 158: ...Programmable I O Pins 12 6...
Page 186: ...Index I 12...