DMA Controller
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Am186™CC/CH/CU Microcontrollers User’s Manual
a general-purpose DMA channel. In source synchronization, the device providing the data
asserts the DMA request.
Figure 8-4 shows a typical source-synchronized DMA transfer. When an external device is
asserting DRQ, the request must be deasserted at least four clock cycles before the end
of the transfer (at T1 of the deposit phase) to prevent another transfer from taking place. If
more transfers are not required, a source-synchronized transfer allows the source device
at least three clock cycles from the time it is acknowledged to deassert its DRQ line. Like
unsynchronized DMA transfers, source-synchronized DMA transfers have the capability of
consuming all bus cycles if the DRQ remains asserted for multiple transfers. An example
of this would be the emptying of a FIFO.
Figure 8-4
Source-Synchronized General-Purpose DMA Transfers
Destination-Synchronized Transfers
Destination-synchronized DMA transfers require either an internally generated DRQ (e.g.,
from a UART transmitter), or an external device that asserts the associated external DRQ
signal for a general-purpose channel. In destination synchronization, the device receiving
the data asserts the DMA request.
Figure 8-5 shows a typical destination-synchronized DMA transfer. The DMA controller
does not sample the DRQ line for a channel until four cycles after the end of the write phase
of a destination-synchronized DMA transfer. This delay allows the external device sufficient
time to remove its request if it does not want another transfer. The delay also allows other
devices access to the bus, including instruction or data fetches by the processor and other
DMA transfers (including transfers by lower priority DMA requests). If another device starts
a bus cycle during the DMA idle cycles, the entire bus cycle completes before giving the
bus back to the DMA. If no other bus activity is initiated, another DMA cycle begins.
Because the DMA controller relinquishes the bus after every destination-synchronized
transfer, the CPU can initiate a bus cycle. As a result, a complete bus cycle is often inserted
T1
T2
T3
T4
T1
T2
T3
T4
CLKOUT
DRQ (First case)
DRQ (Second case)
Fetch Cycle
Fetch Cycle
1
2
Notes:
1. This source-synchronized transfer is not followed immediately by another DMA transfer,
because DRQ is deasserted at least four clock cycles before the end of the transfer.
2. This source-synchronized transfer is immediately followed by another DMA transfer, because
DRQ is not deasserted soon enough.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...