6. Technical Specifications
6.1 Block Diagram
1
2
3
4
A
B
C
D
4
3
2
1
D
C
B
A
POWER
SUPPL
Y
VOL
TAGE
REGULA
TO
R
AC
9V
INPUT
+5V
-5V
Verb
BLOCK
DIAGRAM
MEMOR
Y(DRAM)
(U10,U1
1)
DSP
ED0-ED7
EA0-EA9
AD0-AD7
MPU
(U9
P87C54UBAA)
PROGRAM
SO0
SI0
OUTPUT
L
FOOT
SWITCH
INPUT
R
INPUT
L
(MONO
INPUT)
PJ1
PJ2
PJ5
PJ3
PJ4
VARIA
TIONS
ENCODER
A
STEREO
AUDIO
CODEC
(U6
PCM3001E)
A/D
and
D/A
CONVER
TER
INPUT
BUFFER
&
AMPLIFIER
OUT
-R
OUT
-L
INPUT
LEVEL
OUTPUT
AMPLIFIER
OUTPUT
LEVEL
MIX
CONTROL
LRCKIN=43.20KHZ
BC
K=
1
.
3
82MH
Z
(U8
TMS57002DPHA)
FOOTSWITCH
CONTROL
ENCODER
A
Q1
11.0592MHZ
11.0592MHZ
CLOCK
DIVIDE
(U7
74HC393)
IN-R
IN-L
INPUT
LEVEL
OUTPUT
LEVEL
OUTPUT
R
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