Altera Stratix V GX 100G, Reference Manual

Page: 35 / 76

Chapter 2: Board Components 2–27
General User Input/Output
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
Reference Manual
Table 2–23 lists the user push-button switch component reference and the
manufacturing information.
User DIP Switches
Board references SW4 and SW5 are an 8-pin DIP switch with numbering marked on it
to indicate the switch number. When the switch is in the ON position, a logic 1 is
selected. When the switch is in the OFF position, a logic 0 is selected. The switches are
user-defined and provide additional FPGA input control. There is no board-specific
function for these switches.
Table 2–17 lists the user-defined DIP switch schematic signal names and their
corresponding Stratix V GX pin numbers.
S4
USER_PB0
2.5-V CMOS — MAX II user push button
S9
FPGA_USER_PB3
2.5-V CMOS AM23 FPGA user push button
S10
FPGA_USER_PB2
2.5-V CMOS AW23 FPGA user push button
S11
FPGA_USER_PB1
2.5-V CMOS AR24 FPGA user push button
S12
FPGA_USER_PB0
2.5-V CMOS AU25 FPGA user push button
Table 2–15. User Push Button Signal Names and Functions (Part 2 of 2)
Board
Reference
Schematic
Signal Name
I/O Standard
Stratix V GX Device
Pin Number
Description
Table 2–16. User Push-Button Switch Component References and Manufacturing Information
Board
Reference
Device Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
S2–S4,
S9–S12
Push buttons Panasonic Corporation EVQPAC07K www.panasonic.com
Table 2–17. User-Defined DIP Switch Schematic Signal Names and Functions
Board
Reference
Schematic
Signal Name
I/O Standard
Stratix V GX Device
Pin Number
Description
SW5.1
USER_DIPSW0
2.5-V CMOS —
User-defined DIP switch that connects to
the MAX II CPLD device.
SW5.2
USER_DIPSW1
2.5-V CMOS —
SW5.3
USER_DIPSW2
2.5-V CMOS —
SW5.4
USER_DIPSW3
2.5-V CMOS —
SW5.5
USER_DIPSW4
2.5-V CMOS —
SW5.6
USER_DIPSW5
2.5-V CMOS —
SW5.7
USER_DIPSW6
2.5-V CMOS —
SW5.8
USER_DIPSW7
2.5-V CMOS —