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Altera Stratix V GX 100G, Reference Manual

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Altera Stratix V GX 100G Reference Manual Download Page 23

Chapter 2: Board Components

2–15

MAX II CPLD EPM2210 System Controller

August 2012

Altera Corporation

100G Development Kit, Stratix V GX Edition

Reference Manual

G5

LCD_DATA2

2.5-V

AV11

LCD data

H3

LCD_DATA3

2.5-V

AF31

LCD data

G4

LCD_DATA4

2.5-V

AE12

LCD data

G1

LCD_DATA5

2.5-V

BD20

LCD data

F6

LCD_DATA6

2.5-V

AP31

LCD data

G2

LCD_DATA7

2.5-V

AU11

LCD data

J3

LCD_WEN

2.5-V

AM32

LCD write enable

N17

LINE_SIDE0

2.5-V

—

Spare I/Os on the MAX II CPLD and function as an I/O 
expander for the FPGA. Data can pass through the MAX II 
CPLD to the Stratix V GX interface.

M13

LINE_SIDE1

2.5-V

—

N18

LINE_SIDE2

2.5-V

—

M12

LINE_SIDE3

2.5-V

—

M16

LINE_SIDE4

2.5-V

—

L16

LINE_SIDE5

2.5-V

—

M17

LINE_SIDE6

2.5-V

—

L15

LINE_SIDE7

2.5-V

—

M18

LINE_SIDE8

2.5-V

—

L14

LINE_SIDE9

2.5-V

—

M5

LOAD

2.5-V

—

Initiates a load of the selected image from the PFL

U16

M570_CLOCK

1.5-V

—

25-MHz clock to on-board USB-Blaster II for sending the 
FACTORY command

G12

MAX2_CLK

2.5-V

AW10

MAX II CPLD clock

F17

MAX2_CSN

2.5-V

AG10

MAX II CPLD chip select

F18

MAX2_OEN

2.5-V

AY37

MAX II CPLD output enable

G13

MAX2_WEN

2.5-V

AN12

MAX II CPLD write enable

T16

MAX_CONF_DONEN

2.5-V

—

FPGA configuration done LED. Indicates that the FPGA is 
loaded with the new image.

T17

MAX_ERROR

2.5-V

—

FPGA configuration error LED

R15

MAX_LOAD

2.5-V

—

FPGA configuration active LED

C17

OVERTEMPN

2.5-V

—

Over-temperature indicator from the temperature sense 
circuit

N1

PGM_SEL

2.5-V

—

Push button to select which image to program into the 
FPGA

P3

PHASE60

2.5-V

—

Switch control for the dual 1.5-V and 3.3-V regulators

P2

PHASE120

2.5-V

—

Switch control for the dual 5.0-V and 2.5-V regulators

P4

PHASE180

2.5-V

—

Switch control for the dual 5.0-V and 2.5-V regulators

P1

PHASE240

2.5-V

—

Switch control for the dual 1.5-V and 3.3-V regulators

N4

PWR_CTL

2.5-V

—

Power monitor control

H5

SENSE_CE0

2.5-V

—

Chip select for the first current sense ADC

J2

SENSE_CE1

2.5-V

—

Chip select for the second current sense ADC

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5)

Board 

Reference 

(U59)

Schematic Signal 

Name

I/O 

Standard

Stratix V GX 

Device Pin 

Number

Pin Description

Summary of Contents for Stratix V GX 100G

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com MNL 01066 1 1 Reference Manual 100G Development Kit Stratix V GX Edition Feedback Subscribe...

Page 2: ...oducts to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsi...

Page 3: ...h Memory 2 18 FPGA Programming over External USB Blaster 2 18 Status Elements 2 19 Status LEDs 2 19 Setup Elements 2 21 Board settings DIP switch 2 21 Push Buttons 2 22 Board Jumpers 2 22 Clock Circui...

Page 4: ...ontents 100G Development Kit Stratix V GX Edition August 2012 Altera Corporation Reference Manual Additional Information Document Revision History 1 1 How to Contact Altera 1 1 Typographic Conventions...

Page 5: ...aluating the performance and signal integrity features of the Altera Stratix V GX devices The board features the following major component blocks Stratix V GX FPGA 5SGXEA7N2F45C2N in 1932 pin FineLine...

Page 6: ...ter LCD Ten configuration status LEDs Components and interfaces 10 100 1000 Ethernet PHY and RJ 45 connector USB 2 0 PHY 48 transceiver channels Two channels for SMA interface Four channels for SFP in...

Page 7: ...static handling the board can be damaged Therefore use anti static handling precautions when touching the board The Stratix V GX 100G development board must be stored between 40 C and 100 C The recom...

Page 8: ...1 4 Chapter 1 Overview Handling the Board 100G Development Kit Stratix V GX Edition August 2012 Altera Corporation Reference Manual...

Page 9: ...development board reside in the Stratix V GX 100G development kit installation directory f For information about powering up the board and installing the development kit software refer to the 100G Dev...

Page 10: ...SW6 Interlaken Channel 0 11 J52 J53 Ethernet Status LEDs D12 D17 USB Type B Connector J65 Stratix V GX FPGA U38 Ethernet RJ 45 Connector J7 User Push Buttons S4 S6 FPGA User Push Buttons S7 S10 User D...

Page 11: ...ntroller functions such as clock enable power and temperature monitor as well as voltage settings for transceivers and SMA clock input control U59 MAX II CPLD System Altera EPM2210F324C3N MAX II CPLD...

Page 12: ...he FPGA J64 Character LCD Connector which interfaces to the 16 character 2 line LCD module S2 S4 User push buttons User push buttons that connect to the MAX II CPLD EPM2210 System Controller S9 S12 FP...

Page 13: ...Quad 0 9 V swither Supplies 0 9 V power to the FPGA core and VCCHIP U77 1 5 V linear regulator Supplies 1 5 V power to VCCPT on the FPGA U65 2 5 V switcher Supplies 2 5 V power to VCC_AUX and VCCA on...

Page 14: ...20K Memory Mbits 50 Total Transceiver Channels 48 18 bit 18 bit Multipliers 512 27 bit 27 bit Multipliers 256 PLLs 28 Maximum User I O pins 840 Table 2 3 Stratix V GX Device Component Reference and Ma...

Page 15: ...el SMA_TX_P _N 1 0 Transceiver non inverted inverted output 4 SMA transmit channel Flash FLASH_ADVN 2 5 V LVCMOS output 1 Flash advance input FLASH_CEN 2 5 V LVCMOS output 1 Flash chip enable FLASH_CL...

Page 16: ...QDR II data input QDR2B_BWSN 1 0 1 5 V HSTL output 2 QDR II byte write select QDR2B_WPSN 1 5 V HSTL output 1 QDR II write port select QDR2B_RPSN 1 5 V HSTL output 1 QDR II read port select QDR2B_K_P...

Page 17: ...CFP_MOD_LOPWR 2 5 V LVCMOS output 1 CFP low power mode CFP_MOD_ABS 2 5 V LVCMOS input 1 CFP module absent Interlaken INT_CAP_RX_P _N 23 0 Transceiver non inverted inverted input 48 Interlaken receive...

Page 18: ...8 FPP data FPGA_MSEL 4 0 2 5 V LVCMOS input 5 Dedicated configuration pins FPGA_CONFIGN 2 5 V LVCMOS 1 Dedicated configuration pins FPGA_STATUSN 2 5 V LVCMOS output 1 Dedicated configuration pins FPG...

Page 19: ...evision and board information read only LCD_WEN 2 5 V LVCMOS output 1 LCD write enable Ethernet ENET_TXD 3 0 2 5 V LVCMOS output 4 Ethernet transmit RGMII data bus ENET_TX_EN 2 5 V LVCMOS output 1 Eth...

Page 20: ...ecoder Encoder GPIO JTAG Control Control Register Fast Configuration Downloader Si5338 Programmable Oscillator Table 2 5 MAX II CPLD EPM2210 System Controller Device Pin Out Part 1 of 5 Board Referenc...

Page 21: ...5 V BC39 FPGA configuration data E13 FPGA_DATA3 2 5 V BD37 FPGA configuration data B16 FPGA_DATA4 2 5 V BC38 FPGA configuration data D13 FPGA_DATA5 2 5 V AR37 FPGA configuration data C15 FPGA_DATA6 2...

Page 22: ...lash data F11 FSM_D3 2 5 V BD35 FSM bus flash data C5 FSM_D4 2 5 V AV37 FSM bus flash data D7 FSM_D5 2 5 V AV35 FSM bus flash data F7 FSM_D6 2 5 V AL9 FSM bus flash data C6 FSM_D7 2 5 V AF13 FSM bus f...

Page 23: ...ock F17 MAX2_CSN 2 5 V AG10 MAX II CPLD chip select F18 MAX2_OEN 2 5 V AY37 MAX II CPLD output enable G13 MAX2_WEN 2 5 V AN12 MAX II CPLD write enable T16 MAX_CONF_DONEN 2 5 V FPGA configuration done...

Page 24: ...5 1 5 V AT17 On board USB Blaster II data U4 USB_CFG6 1 5 V BD19 On board USB Blaster II data T6 USB_CFG7 1 5 V AN23 On board USB Blaster II data N3 USER1_POF 2 5 V LED to Indicate which user pof file...

Page 25: ...e following sections describe each of these methods FPGA Programming over On Board USB Blaster II The USB Blaster II is implemented using a USB type B connector J5 a USB 2 0 PHY device and an Altera M...

Page 26: ...m for the MAX II Flash FPP configuration Additionally ten green configuration status LEDs D24 D29 and D31 D34 indicate the FPP configuration status After configuration completes you can determine whic...

Page 27: ...ng Header StratixV GX JTAG Programming Header Jumper to remove the MAX II CPLD from JTAG programming header TDI TMS TCK LAST_TDO S4GT_TDI S4GT_TDO JTAG_TMS JTAG_TCK JTAG_TMS JTAG_TCK MAX_FPP_TDI MAX_F...

Page 28: ...is successfully configured Driven by the FPGA D24 MAX_ERR MAX_ERROR 2 5 V CMOS Red LED Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA Driven by the MAX II CPLD...

Page 29: ...PLL input Selects SMA or PLL for the differential clock that goes to the global clock inputs of clock A tree structure 3 REFCLKA_SEL 2 5 V 1 SMA input 0 PLL input Selects SMA or PLL that goes to the...

Page 30: ...ists the push buttons component references and the manufacturing information Board Jumpers The board jumpers control feature specific to the JTAG chain and the MAXII CPLD EPM2210 System Controller log...

Page 31: ...erlaken interface and the DDR3 interface uses one programmable on board quad PLL to generate the necessary frequencies The default frequency for the Interlaken interface is 625 MHz and for the DDR3 in...

Page 32: ...I O Standard Stratix V GX Device Pin Name Description DIFFCLK_IN1_N P LVDS BA34 AY34 Differential programmable clock to I O bank 3B CLKIN_125_N P LVDS BA18 AY18 Differential fixed clock to I O bank 3...

Page 33: ...reference clocks for the FPGA fabric REFCLK_OSC_N P LVDS SMA input to FPGA reference clocks for transceivers to optical interfaces SMA_REF_CLKIN_N P LVDS SMA input to FPGA reference clocks for transce...

Page 34: ...ush buttons that allow you to interact with the MAX II CPLD device and the Stratix V GX device When you press the switch and hold it down the device pin is set to logic 0 When you release the switch t...

Page 35: ...0 FPGA_USER_PB2 2 5 V CMOS AW23 FPGA user push button S11 FPGA_USER_PB1 2 5 V CMOS AR24 FPGA user push button S12 FPGA_USER_PB0 2 5 V CMOS AU25 FPGA user push button Table 2 15 User Push Button Signal...

Page 36: ...User defined DIP switch that connects to the FPGA device SW4 2 FPGA_USER_DIPSW1 2 5 V CMOS BC7 SW4 3 FPGA_USER_DIPSW2 2 5 V CMOS AE13 SW4 4 FPGA_USER_DIPSW3 2 5 V CMOS AG21 SW4 5 FPGA_USER_DIPSW4 2 5...

Page 37: ...R_LED2 2 5 V CMOS AN14 D49 FPGA_USER_LED1 2 5 V CMOS AT27 D50 FPGA_USER_LED0 2 5 V CMOS AU27 Table 2 19 User Defined LED Schematic Signal Names and Functions Part 2 of 2 Board Reference Schematic Sign...

Page 38: ...edded NIOS applications Table 2 24 provides the pin out information of the flash memory interface to the FPGA The signal direction is with respect to the FPGA device Table 2 22 LCD Pin Definitions and...

Page 39: ...lash address bus A5 FSM_A13 2 5 V CMOS AE29 Flash address bus B5 FSM_A14 2 5 V CMOS AW22 Flash address bus C5 FSM_A15 2 5 V CMOS AN36 Flash address bus D7 FSM_A16 2 5 V CMOS AW9 Flash address bus D8 F...

Page 40: ...ilize 46 transceiver channels There are eight channels on the QSFP interface four independent channels on the SFP 10 channels on the CFP interface and 24 channels that make up the Interlaken interface...

Page 41: ...absent 8 QSFP0_MOD_SELN 2 5 V LVCMOS AK20 Module select input 0 Select module for two wire serial communication 1 Module not available for two wire serial communication 9 QSFP0_RST 2 5 V LVCMOS BC35 M...

Page 42: ...h power mode 1 Set module for low power mode maximum power consumption is 1 5 W 27 QSFP1_MOD_PRSN 2 5 V LVCMOS AV22 Module present output 0 Module present inserted 1 Module absent 8 QSFP1_MOD_SELN 2 5...

Page 43: ...e Description Manufacturer Manufacturing Part Number Manufacturer Website J33 J19 Single port family standard QSFP cage right angle press fit connector Tyco Electronics 1888617 1 www te com Table 2 29...

Page 44: ...P2_MOD1_SCL 2 5 V LVCMOS AN33 Two wire serial interface clock line 24 SFP2_MOD2_SDA 2 5 V LVCMOS AE30 Two wire serial interface data line 27 SFP2_RATESEL 2 5 V LVCMOS BD10 Rate select Controls the SFP...

Page 45: ...DISABLE 2 5 V LVCMOS AH10 Turns off and disables the transmitter laser output 2 SFP3_TXFAULT 2 5 V LVCMOS AU22 Interface transmitter fault Table 2 29 SFP Interface Pin Assignments Schematic Signal Nam...

Page 46: ...power interlock LSB 00 8 W 01 16 W 10 24 W 11 or NC 24 W or not in use 32 CFP_PRG_CNTL3 2 5 V LVCMOS AW21 Programmable control 3 set via MDIO and MSA for hardware power interlock MSB 00 8 W 01 16 W 1...

Page 47: ...O port address 45 CFP_T_PRTADR1 2 5 V LVCMOS MDIO port address 44 CFP_T_PRTADR2 2 5 V LVCMOS MDIO port address 43 CFP_T_PRTADR3 2 5 V LVCMOS MDIO port address 42 CFP_T_PRTADR4 2 5 V LVCMOS MDIO port a...

Page 48: ...V PCML J4 Transmit XCVR pair 9 from FPGA 141 CFP_TX_N9 1 5 V PCML J3 Transmit XCVR pair 9 from FPGA Table 2 31 CFP Interface Pin Assignments Schematic Signal Names and Functions Part 4 of 4 Board Refe...

Page 49: ...X_P10 1 5 V PCML AJ41 Transmit XCVR pair 10 from FPGA K4 INT_TX_N10 1 5 V PCML AJ42 Transmit XCVR pair 10 from FPGA G1 INT_TX_P11 1 5 V PCML AV39 Transmit XCVR pair 11 from FPGA H1 INT_TX_N11 1 5 V PC...

Page 50: ...clock for the second 12 bits of the bus E10 INT_MSB_CON_TX_FC_CK 2 5 V LVCMOS AK33 Transmit flow control clock signal for the second 12 bits of the bus H7 INT_MSB_CON_TX_FC_DATA 2 5 V LVCMOS AE36 Tran...

Page 51: ...2 bits of the bus H9 INT_MSB_CON_RX_FC_SYNC 2 5 V LVCMOS BD11 Receive flow control synchronization signal for the second 12 bits of the bus A7 INT_RX_P12 1 5 V PCML B43 Receive XCVR pair 12 to FPGA B7...

Page 52: ...get speed is 800 MHz DDR for a theoretical bandwidth of over 51 2 Gbps per 32 bit port or a total bandwidth of 307 2 Gbps for the full 192 bit bus The targeted Micron device is rated at 800 MHz with a...

Page 53: ...dress bus R3 DDR3A_A9 1 5 V SSTL P12 Address bus L7 DDR3A_A10 1 5 V SSTL N8 Address bus R7 DDR3A_A11 1 5 V SSTL K10 Address bus N7 DDR3A_A12 1 5 V SSTL K9 Address bus T3 DDR3A_A13 1 5 V SSTL U14 Addre...

Page 54: ...V SSTL U9 Data strobe P byte lane 0 G3 DDR3A_DQS_N0 1 5 V SSTL T9 Data strobe N byte lane 0 C7 DDR3A_DQS_P1 1 5 V SSTL K11 Data strobe P byte lane 1 B7 DDR3A_DQS_N1 1 5 V SSTL L11 Data strobe N byte l...

Page 55: ...SSTL H13 Data bus F2 DDR3B_DQ2 1 5 V SSTL F13 Data bus F8 DDR3B_DQ3 1 5 V SSTL K13 Data bus H3 DDR3B_DQ4 1 5 V SSTL H15 Data bus H8 DDR3B_DQ5 1 5 V SSTL H14 Data bus G2 DDR3B_DQ6 1 5 V SSTL G14 Data b...

Page 56: ...B_ODT 1 5 V SSTL U12 On die termination J3 DDR3B_RASN 1 5 V SSTL B17 Row address select T2 DDR3B_RSTN 1 5 V SSTL V16 Reset L3 DDR3B_WEN 1 5 V SSTL K18 Write enable DDR3 Port C Interface U26 U33 N3 DDR...

Page 57: ...DDR3C_DQ14 1 5 V SSTL D17 Data bus A3 DDR3C_DQ15 1 5 V SSTL H16 Data bus E3 DDR3C_DQ16 1 5 V SSTL A17 Data bus F7 DDR3C_DQ17 1 5 V SSTL A19 Data bus F2 DDR3C_DQ18 1 5 V SSTL C18 Data bus F8 DDR3C_DQ1...

Page 58: ...C25 Address bus R2 DDR3D_A7 1 5 V SSTL R24 Address bus T8 DDR3D_A8 1 5 V SSTL D24 Address bus R3 DDR3D_A9 1 5 V SSTL T24 Address bus L7 DDR3D_A10 1 5 V SSTL G23 Address bus R7 DDR3D_A11 1 5 V SSTL D23...

Page 59: ...STL M27 Data bus C2 DDR3D_DQ27 1 5 V SSTL N28 Data bus A7 DDR3D_DQ28 1 5 V SSTL P26 Data bus A2 DDR3D_DQ29 1 5 V SSTL P27 Data bus B8 DDR3D_DQ30 1 5 V SSTL N26 Data bus A3 DDR3D_DQ31 1 5 V SSTL P29 Da...

Page 60: ...s select K7 DDR3E_CK_N 1 5 V SSTL K25 Clock input N J7 DDR3E_CK_P 1 5 V SSTL K26 Clock input P K9 DDR3E_CKE 1 5 V SSTL E30 Clock enable L2 DDR3E_CSN 1 5 V SSTL H24 Chip select E3 DDR3E_DQ0 1 5 V SSTL...

Page 61: ...byte lane 1 F3 DDR3E_DQS_P2 1 5 V SSTL J30 Data strobe P byte lane 2 G3 DDR3E_DQS_N2 1 5 V SSTL H30 Data strobe N byte lane 2 C7 DDR3E_DQS_P3 1 5 V SSTL T30 Data strobe P byte lane 3 B7 DDR3E_DQS_N3 1...

Page 62: ...Data bus H7 DDR3F_DQ7 1 5 V SSTL C36 Data bus D7 DDR3F_DQ8 1 5 V SSTL V34 Data bus C3 DDR3F_DQ9 1 5 V SSTL V33 Data bus C8 DDR3F_DQ10 1 5 V SSTL U32 Data bus C2 DDR3F_DQ11 1 5 V SSTL U33 Data bus A7...

Page 63: ...T32 Data strobe N byte lane 1 F3 DDR3F_DQS_P2 1 5 V SSTL H35 Data strobe P byte lane 2 G3 DDR3F_DQS_N2 1 5 V SSTL G35 Data strobe N byte lane 2 C7 DDR3F_DQS_P3 1 5 V SSTL U35 Data strobe P byte lane...

Page 64: ...5 V HSTL AF28 Byte write select B5 QDR2A_BWSN3 1 5 V HSTL AE28 Byte write select A1 QDR2A_CQ_N 1 5 V HSTL BC28 QDR II echo clock A11 QDR2A_CQ_P 1 5 V HSTL AH27 QDR II echo clock P10 QDR2A_D0 1 5 V HST...

Page 65: ...J31 Write data bus P2 QDR2A_D35 1 5 V HSTL AJ30 Write data bus A6 QDR2A_K_N 1 5 V HSTL BB32 QDR II clock input B6 QDR2A_K_P 1 5 V HSTL BA31 QDR II clock input B10 QDR2A_Q0 1 5 V HSTL BD29 Read data bu...

Page 66: ...P1 QDR2A_Q35 1 5 V HSTL AH25 Read data bus A8 QDR2A_RPSN 1 5 V HSTL AT24 Read port select A4 QDR2A_WPSN 1 5 V HSTL AU23 Write port select QDRII Port B Interface U40 R9 QDR2B_A0 1 5 V HSTL AU18 Address...

Page 67: ...TL AJ14 Write data bus D2 QDR2B_D11 1 5 V HSTL AH15 Write data bus F3 QDR2B_D12 1 5 V HSTL AG16 Write data bus G2 QDR2B_D13 1 5 V HSTL AG15 Write data bus J3 QDR2B_D14 1 5 V HSTL AG14 Write data bus L...

Page 68: ...us K3 QDR2B_Q14 1 5 V HSTL AL15 Read data bus L2 QDR2B_Q15 1 5 V HSTL AL14 Read data bus N3 QDR2B_Q16 1 5 V HSTL AJ13 Read data bus P3 QDR2B_Q17 1 5 V HSTL AH13 Read data bus A8 QDR2B_RPSN 1 5 V HSTL...

Page 69: ...eceive data active LED 61 ENET_LED_TX 2 5 V LVCMOS Ethernet transmit data active LED 68 ENET_LED_TX 2 5 V LVCMOS Ethernet transmit data active LED 25 ENET_MDC 2 5 V LVCMOS AP39 Ethernet management bus...

Page 70: ...ower is provided through a laptop style DC power input The input voltage must be 19 V The DC voltage is then stepped down to various power rails used by the components on the board 42 MDI_P3 2 5 V LVC...

Page 71: ...I DDR3 VCC_IO 2 5V_VCCA_PLL VCCT_GXB VCCR_GXB 2 5VIO_PD_CLK_PGM 1 5V_VCCPT VCCH_GXB VCC VCCHSSI VCCHIP QSFP SFP VCCD_PLL CFP Translators Flash QDR II VCCA_GXB LTM4601 Switcher LTM4601 Switcher LT1374...

Page 72: ...y SCK DSI DSO CSn 8 Ch To Plane To Plane Supply 0x0 Supply 0xE RSENSE RSENSE SCK DSI DSO CSn 8 Ch MAX II CPLD LTC2418 LTC2418 U41 EPM570 USB To User PC Power GUI JTAG Chain SPI Bus On Board USB Blaste...

Page 73: ...1A parallelable LDO 1 2 V 36 V input 0 V 36 V output 300 mV dropout 40 UVRMS DFN 8 Linear Technology LT3080EDD 1 PBF www linear com U15 U16 U17 U18 Regulator 15 A DC DC module VIN 4 5 V 20 V VOUT 0 6...

Page 74: ...2 66 Chapter 2 Board Components Statement of China RoHS Compliance 100G Development Kit Stratix V GX Edition August 2012 Altera Corporation Reference Manual...

Page 75: ...ntact Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www altera com literature...

Page 76: ...eyword SUBDESIGN and logic function names for example TRI r An angled arrow instructs you to press the Enter key 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of...

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