Altera CLR-HSMC Page 10 User Manual Download | Manualshive

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Figure 2-8

Camera Link Receiver Card connection to Altera DE4 Development and Education Board

Note. An adapter (HMF2) is required to connect CLR-HSMC with DE4. It is bundled in DE4 kit.

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Summary of Contents for CLR-HSMC

Page 1: ...1 ...

Page 2: ...4 COMPONENTS 18 U4 1 LVDS 28 Bit Channel LinkU 18 U4 2 3V LVDS Quad CMOS Differential Line DriverU 18 U4 3 Operation ModeU 18 UCHAPTER 5 DEMONSTRATIONS 21 U5 1 Digital Camera Demonstration for DE4U 21 U5 2 Digital Camera Demonstration for DE3U 23 U5 3 Digital Camera Demonstration for DE2 115U 25 U5 4 Digital Camera with PCI Express Interface for DE4U 27 UCHAPTER 6 APPENDIX 30 U6 1 Revision History...

Page 3: ...E2 115 1 1 1 1 F Fe ea at tu ur re es s XFigure 1 1X shows the photo of the CLR HSMC board The important features are listed below Support of standard Camera Link modes base medium dual base assembly Serial Communication with camera Simple interface Automatic detection by hardware software Two LVDS 28 bit channel link chip DS90CR288A 28 bit 20 to 85 MHz shift clock support Up to 2 38 Gbps throughp...

Page 4: ...f the CLR HSMC Board 1 1 2 2 G Ge et tt ti in ng g H He el lp p Here are some places to get help if you encounter any problem Email to support terasic com Taiwan China 886 3 550 8800 Korea 82 2 512 7661 Japan 81 428 77 7000 ...

Page 5: ...ration of the CLR HSMC board including block diagram and components Figure 2 1 The CLR HSMC Board PCB and Component Diagram A photograph of the CLR HSMC is shown in XFigure 2 1X and X Figure 2 2X It depicts the layout of the board and indicates the location of the connectors and key components ...

Page 6: ...o LVTTL adapting of data signals U1 U3 National Semiconductor DS90LV047A for LVDS to LVTTL adapting of control signals U5 U7 National Semiconductor DS90LV019 for LVDS to LVTTL adapting of serial control signals U4 U6 2 2 1 1 B Bl lo oc ck k D Di ia ag gr ra am m XFigure 2 3X shows the block diagram of the CLR HSMC board in base mode configuration ...

Page 7: ...Figure 2 3 Block Diagram of the CLR HSMC Board Base Mode XFigure 2 4X shows the block diagram of the CLR HSMC board in medium mode configuration Figure 2 4 Block Diagram of the CLR HSMC Board Medium Mode ...

Page 8: ...LR HSMC board in dual base mode configuration Figure 2 5 Block Diagram of the CLR HSMC Board Dual base Mode 2 2 2 2 C Co on nn ne ec ct ti iv vi it ty y The CLR HSMC offers connectivity to any HSMC based host boards including the DE4 DE3 and DE2 115 ...

Page 9: ...iver Card connection to the Altera DE2 115 Development Board Figure 2 7 Camera Link Receiver Card connection to the Altera DE3 Development System Note An adapter HFF is required to connect CLR HSMC with DE3 It is bundled in DE3 kit ...

Page 10: ...9 Figure 2 8 Camera Link Receiver Card connection to Altera DE4 Development and Education Board Note An adapter HMF2 is required to connect CLR HSMC with DE4 It is bundled in DE4 kit ...

Page 11: ...Ex xp pa an ns si io on n C Co on nn ne ec ct to or r The CLR HSMC board contains a HSMC connector XFigure 3 1X XFigure 3 2X and XFigure 3 3X show the pin outs of the HSMC connector on the CLR HSMC board The voltage level of the I O pin on the HSMC connector can support to 3 3V and 2 5V because the DS90CR288A VIH are as low as 2 0V Please refer to the DS90CR288A s datasheets ...

Page 12: ...11 Figure 3 1 Pin outs of Bank 1 on the HSMC Connector ...

Page 13: ...12 Figure 3 2 Pin outs of Bank 2 on the HSMC Connector ...

Page 14: ...13 Figure 3 3 Pin outs of Bank 3 on the HSMC Connector ...

Page 15: ...utput data 5 50 rx_base10 Output Base output data 10 51 VCC3P3 Power Power 3 3V 52 VCC12 Power Power 12V 53 rx_base6 Output Base output data 6 54 rx_base12 Output Base output data 12 55 rx_base11 Output Base output data 11 56 rx_base13 Output Base output data 13 57 VCC3P3 Power Power 3 3V 58 VCC12 Power Power 12V 59 rx_base16 output Base output data 12 60 rx_base14 output Base output data 14 61 rx...

Page 16: ...l output data 14 90 rxSerTC Input SERTC serial data from HSTC to Camera 91 rx_medium1 Output Medium output data 1 92 rxSerTC_en Input SERTC Driver Enable 1 Enable 0 Disable 93 VCC3P3 Power Power 3 3V 94 VCC12 Power Power 12V 95 rx_medium2 Output Medium output data 2 96 rxclk_base Output Receiver base clock 97 rx_medium3 Output Medium output data 3 98 rxclk_full Output Receiver full clock 99 VCC3P3...

Page 17: ...r enable pin for Dual Base Mode only 123 VCC3P3 Power Power 3 3V 124 VCC12 Power Power 12V 125 rx_medium12 Output Medium output data 12 126 rx_medium0 Output Medium output data 0 127 rx_medium13 Output Medium output data 13 128 rx_medium27 Output Medium output data 27 129 VCC3P3 Power Power 3 3V 130 VCC12 Power Power 12V 131 rx_medium14 Output Medium output data 14 132 rx_medium26 Output Medium ou...

Page 18: ...ll12_hsmc Output Full output data 12 151 rx_medium20 Output Medium output data 20 152 rx_full13_hsmc Output Full output data 13 153 VCC3P3 Power Power 3 3V 154 VCC12 Power Power 12V 155 rx_medium22 Output Medium output data 22 156 rxclk_medium Output Receiver medium clock 157 rx_medium24 Output Medium output data 24 158 rx_full27_hsmc Output Full output data 27 159 VCC3P3 Power Power 3 3V 160 GND ...

Page 19: ... VD DS S Q Qu ua ad d C CM MO OS S D Di if ff fe er re en nt ti ia al l L Li in ne e D Dr ri iv ve er r The CLR board features two National Semiconductor DS90LV047A 3V LVDS quad CMOS differential line driver chip for LVCMOS signals to LVDS signals adapting It is used to transport the control signals to the CameraLink ports Some of the key features are listed below Four LVDS channels with enable co...

Page 20: ... out Serial to Frame Grabber 7 SERTC out 20 SERTC out Serial to Camera 8 X3 in 21 X3 in CameraLink data 3 base 9 CLKX in 22 CLKX in Camera Link clock base 10 X2 in 23 X2 in CameraLink data 2 base 11 X1 in 24 X1 in CameraLink data 1 base 12 X0 in 25 X0 in CameraLink data 0 base 13 Inner Shield 26 Inner Shield Table 4 2 CameraLink Medium configuration J1 Pin Signal Pin Signal Remarks 1 Inner Shield ...

Page 21: ...ut 17 CC2 out Camera Control 2 5 CC1 out 18 CC1 out Camera Control 1 6 SERTFG in 19 SERTFG out Serial to Frame Grabber 7 SERTC out 20 SERTC out Serial to Camera 8 X3 in 21 X3 in CameraLink data 3 base 9 CLKX in 22 CLKX in CameraLink clock base 10 X2 in 23 X2 in CameraLink data 2 base 11 X1 in 24 X1 in CameraLink data 1 base 12 X0 in 25 X0 in CameraLink data 0 base 13 Inner Shield 26 Inner Shield ...

Page 22: ...e er ra a D De em mo on ns st tr ra at ti io on n f fo or r D DE E4 4 The example demonstrates a combinational application of digital Camera Link camera and Camera Link Interface Card on DE4 board In this demo we set the camera to work under Double Speed Operation Mode DIP Switch setting with internal sync and the others at factory default settings And the CLR is configured to base mode The camera...

Page 23: ...rface cards separately which are bundled in the DE4 kit 2 Insert the DDR2 memory card into J9 DDR2 SO DIMM 1 3 Connect the DVI TX output of the DVI daughter card to a DVI monitor with a DVI cable and the camera to BASE1 J2 the CLR card with a Camera Link cable 4 Copy the directory DE4_230 530_CLR from CLR HSMC System CD ROM to the host computer 5 Download the bitstream DE4_230 530_CLR sof to the D...

Page 24: ... at factory default settings And the CLR is configured to base mode The camera outputs Camera Link Interface specification data to DE3 via the CLR Card According to XFigure 5 3X the CCD_Capture module captures one frame video streams with sync signals then the RAW2RGB module converts them to RGB format After that the frame buffer caches the frame data and sends them to be displayed on a DVI interf...

Page 25: ...face card which are bundled in the DE3 kit 2 Insert the DDR2 memory card into J9 DDR2 SO DIMM 3 Connect the DVI TX output of the DVI daughter card to a DVI monitor with a DVI cable and the camera to BASE1 J2 of the CLR card with a Camera Link cable 4 Copy the directory DE3_150 260 340_CLR from CLR HSMC System CD ROM to the host computer 5 Download the bitstream DE3_150 260 340_CLR sof to the DE3 b...

Page 26: ...rs at factory default settings And the CLR is configured to dual base mode The camera outputs Camera Link Interface specification data to DE2 115 via the CLR Card According to X Figure 5 5X the CCD_Capture module captures one frame video streams with sync signals then the RAW2RGB module converts them to RGB format After that the frame buffer caches the frame data and sends them to be displayed on ...

Page 27: ...XFigure 5 6X Make sure the CLR Card is connected to JP8 HSMC of the DE2 115 board 2 Connect the VGA output of DE2 115 board to a VGA monitor and the camera to BASE1 J2 of the CLR card with a Camera Link cable 3 Copy the directory DE2_115_CLR from CLR HSMC System CD ROM to the host computer 4 Download the bitstream DE2_115_CLR sof to the DE2 115 board 5 Set the SW 0 to On upper position to show the...

Page 28: ...with DE4 board via PCIe interface and can perform better real time display of the video frames The system block diagram is shown in XFigure 5 7X In this demo we set the camera to work under Double Speed Operation Mode DIP Switch setting with internal sync and the others at factory default settings And the CLR is configured to base mode The image resolution is 640x480 and the data transfer rate is ...

Page 29: ...ection is made correctly as shown in XFigure 5 8X Make sure the CLR Card is connected to J21 HSMC PORT B and with two THCB HMF2 interface cards which are bundled in the DE4 kit 2 Insert the DDR2 memory card into J9 DDR2 SO DIMM and turn on the PCIe X8 detection SW9 3 Connect a camera to BASE1 J2 of the CLR card with a Camera Link cable 4 Install the DE4 board on the PC 5 Copy the directory DE4_230...

Page 30: ...29 Figure 5 8 Setup for PCI Express Application for Digital Camera Link on DE4 XFigure 5 9X shows the Terasic PCIe monitor PC program Figure 5 9 Terasic PCI Monitor ...

Page 31: ...Add support 2 5 V and 3 3V IO standard description 6 6 2 2 C Co op py yr ri ig gh ht t S St ta at te em me en nt t Always visit CLR_HSMC webpage for new applications We will be continuing providing interesting examples and labs on our CLR_HSMC webpage Please visit HUwww altera comUH or HUclr terasic comUH for more information Copyright 2010 Terasic Technologies All rights reserved ...

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