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FMC-CAMERALINK User Manual

V2.7 - 5th February 2019

Figure 1

FMC-CAMERALINK Block Diagram .................................................................................................. 1

Figure 2

FMC-CAMERALINK .......................................................................................................................... 2

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Summary of Contents for FMC-CAMERALINK

Page 1: ...FMC CAMERALINK User Manual Document Revision 2 7 5th February 2019...

Page 2: ...ape or form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address 4 West Silvermills Lane Edinburgh EH3 5BD UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sale...

Page 3: ...6 PoCL 15 6 1 Current limit 15 6 2 Notes 15 7 RS232 Electrical Specifications 16 List of Tables Table 1 FMC CAMERALINK board features 2 Table 2 Camera Link Connector 1 Dual Base Input Configuration 5...

Page 4: ...FMC CAMERALINK User Manual V2 7 5th February 2019 Figure 1 FMC CAMERALINK Block Diagram 1 Figure 2 FMC CAMERALINK 2...

Page 5: ...um or Full configuration input In addition to being able to be used for image capture the FMC CAMERALINK may also be used for emulation of either up to two Base format cameras or one Medium Full forma...

Page 6: ...number 1SF26 L120 00C XXX where XXX length in centimetres SDR to MDR cable assembly 3M part number 1MF26 L560 00C XXX where XXX length in centimetres Auxiliary Serial 0 1 2 54mm pitch female plug 2 4...

Page 7: ...oard 3 2 IO Voltage Selection The host board is required to provide FMC_VADJ in the range 1 8V to 3 3V with 1 8V preferred This requirement is stored in a ROM on the FMC as per VITA 57 1 for automatic...

Page 8: ...CAMERALINK The FMC does not support providing power over the Camera Link Connection 4 2 FMC CAMERALINK PoCL Power can be provided by the FMC CAMERALINK over the Camera Link connection s to attached ca...

Page 9: ...n SDR pin Con 1 xclk_p in LA_P_00 9 xclk_n in LA_N_00 22 x_p 0 in LA_P_02 12 x_n 0 in LA_N_02 25 x_p 1 in LA_P_03 11 x_n 1 in LA_N_03 24 x_p 2 in LA_P_04 10 x_n 2 in LA_N_04 23 x_p 3 in LA_P_05 8 x_n...

Page 10: ...n LA_N_08 23 x_p 3 in LA_P_09 8 x_n 3 in LA_N_09 21 cc_p 1 out LA_P_11 5 cc_n 1 out LA_N_11 18 cc_p 2 out LA_N_12 17 cc_n 2 out LA_P_12 4 cc_p 3 out LA_P_17 3 cc_n 3 out LA_N_17 16 cc_p 4 out LA_N_13...

Page 11: ...25 x_p 1 in LA_P_03 11 x_n 1 in LA_N_03 24 x_p 2 in LA_P_04 10 x_n 2 in LA_N_04 23 x_p 3 in LA_P_05 8 x_n 3 in LA_N_05 21 cc_p 1 out LA_P_18 5 cc_n 1 out LA_N_18 18 cc_p 2 out LA_P_19 17 cc_n 2 out LA...

Page 12: ...24 y_p 2 in LA_P_08 10 y_n 2 in LA_N_08 23 y_p 3 in LA_P_09 8 y_n 3 in LA_N_09 21 zclk_p in LA_P_17 3 zclk_n in LA_N_17 16 z_p 0 in LA_P_10 6 z_n 0 in LA_N_10 19 z_p 1 in LA_P_11 5 z_n 1 in LA_N_11 1...

Page 13: ..._p 1 out LA_N_20 16 x_n 1 out LA_P_20 3 x_p 2 out LA_P_19 17 x_n 2 out LA_N_19 4 x_p 3 out LA_N_14 19 x_n 3 out LA_P_14 6 cc_p 1 in LA_N_00 22 cc_n 1 in LA_P_00 9 cc_p 2 in LA_P_04 10 cc_n 2 in LA_N_0...

Page 14: ...2 out LA_P_12 4 x_p 3 out LA_N_10 19 x_n 3 out LA_P_10 6 cc_p 1 in LA_N_01 22 cc_n 1 in LA_P_01 9 cc_p 2 in LA_P_08 10 cc_n 2 in LA_N_08 23 cc_p 3 in LA_N_07 24 cc_n 3 in LA_P_07 11 cc_p 4 in LA_P_06...

Page 15: ...1 2 x_p 1 out LA_N_20 16 x_n 1 out LA_P_20 3 x_p 2 out LA_P_19 17 x_n 2 out LA_N_19 4 x_p 3 out LA_N_14 19 x_n 3 out LA_P_14 6 cc_p 1 in LA_N_00 22 cc_n 1 in LA_P_00 9 cc_p 2 in LA_P_04 10 cc_n 2 in L...

Page 16: ...2 out LA_N_12 17 y_n 2 out LA_P_12 4 y_p 3 out LA_N_10 19 y_n 3 out LA_P_10 6 zclk_p out LA_N_07 24 zclk_n out LA_P_07 11 z_p 0 out LA_N_09 21 z_n 0 out LA_P_09 8 z_p 1 out LA_N_01 22 z_n 1 out LA_P_...

Page 17: ...used for synchronising between FPGA boards where multiple FMC CAMERALINKs are used Signal Name Direction FMC pin Notes J1 inout LA_N_32 Un buffered general purpose IO J2 inout LA_N_33 Un buffered gene...

Page 18: ...nvalid_l in LA_P_33 Legacy Has behaviour matching ready Table 12 RS232 Interface Signal Name Direction JP1 pin Notes txmon out 1 RS232 compatible output gnd 2 Ground rxmon in 3 RS232 compatible input...

Page 19: ...or disable power pocl_fault_a_l in LA_N_22 Logic level 0 indicates a PoCL fault for Connector 1 when pocl_en_a_l is enabled pocl_fault_b_l in LA_N_23 Logic level 0 indicates a PoCL fault for Connecto...

Page 20: ...put Voltage Range 25 25 V Input Threshold Low 0 6 1 2 V Input Threshold High 1 5 2 4 V Input Hysteresis 0 5 V Input Resistance 3 5 7 k Table 15 RX input TX Outputs Min Typ Max Units Output Voltage Swi...

Page 21: ...ed documentation for PoCL Builds 29 June 2015 2 3 Clarified PoCL and auxiliary serial functionality 13th Mar 2017 2 4 Correct polatiry of LA_N_06 LA_P_06 in Camera Link Connector 2 Base Medium Full Ou...

Page 22: ...ills Lane Edinburgh EH3 5BD UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales alpha data com website http www alpha data com Address 611 Corporate Circle Suite H Golden CO 80401 Telephone 3...

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