FMC-CAMERALINK User Manual
V2.7 - 5th February 2019
5.1.2 Base/Medium/Full Input Configuration
The following tables show the pin usage for attaching one Base/Medium or Full camera to an FPGA design.
Signal Name
Direction
FMC pin
SDR pin (Con. 1)
xclk_p
in
LA_P_00
9
xclk_n
in
LA_N_00
22
x_p<0>
in
LA_P_02
12
x_n<0>
in
LA_N_02
25
x_p<1>
in
LA_P_03
11
x_n<1>
in
LA_N_03
24
x_p<2>
in
LA_P_04
10
x_n<2>
in
LA_N_04
23
x_p<3>
in
LA_P_05
8
x_n<3>
in
LA_N_05
21
cc_p<1>
out
LA_P_18
5
cc_n<1>
out
LA_N_18
18
cc_p<2>
out
LA_P_19
17
cc_n<2>
out
LA_N_19
4
cc_p<3>
out
LA_P_20
3
cc_n<3>
out
LA_N_20
16
cc_p<4>
out
LA_P_21
15
cc_n<4>
out
LA_N_21
2
ser_tfg_p
in
LA_P_14
6
ser_tfg_n
in
LA_N_14
19
ser_tc_p
out
LA_P_15
20
ser_tc_n
out
LA_N_15
7
Table 4 : Camera Link Connector 1 (Base/Medium/Full Input Configuration)
Page 7
Pin-out
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