ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020
3.2 VPX P0 Interface
3.2.1 SYSRESET#
VPX Reset In. This signal is an active low input from the system. When asserted, the PS PCIe interface will be
reset.
The SYSRESET# signal is translated to 1.8V levels and connected to the FPGA at MIO pin J22.
3.2.2 AUXCLK
Auxiliary Clock. This clock is a direct input to the target FPGA. In OpenVPX this clock line is used for 1PPS
synchronization signaling. The prefered signaling standard is LVDS.
AUXCLK_P is connected to FPGA GC pin E22
AUXCLK_N is connected to FPGA GC pin D22
3.2.3 REFCLK
Reference Clock. This clock is an input to the onboard clock distribution and generation system. The 50MHz
defined in OpenVPX can be used to align all system clocks. Alternatively an onboard 25MHz reference can be
VPX Control Switch Definitions (SW3)
.
3.3 VPX P2 GPIO
3.3.1 LVDS
The GPIO on P2 is compatible with 2.5V signaling such as LVDS and 2.5V single ended signals.
These signals are routed differentially. The FPGA is protected from inappropriate signal levels by a low
resistance quick switch that clamps at 2.5V in either direction, but can accept up to 3.3V on an input.
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Functional Description
ad-ug-1323_v1_1.pdf
