Alpha Data ADM-PCIE-KU3, User Manual

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ADM-PCIE-KU3 User Manual
3.3 PCI Express
The ADM-PCIE-KU3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes (where 16-lanes requires a two
bifurcated 8-lane interfaces). The FPGA drives these lanes directly using the Integrated PCI Express block from
Xilinx. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user
intervention.
PCI Express reset (PERST#) connected to the FPGA at both pins N23 and K22. Do not configure these pins as
outputs and do not add a pull-up constraint.
Note:
The Xilinx IP core automatically instantiates a pull-up on PERST#, this MUST be removed for the reset pin to
function correctly.
Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" to "chip-to-chip".
The other pin assignments for the high speed lanes are provided in the table below:
Signal Target FPGA Input P pin N pin
PCIE_TX0 MGTHTX3_225 AC4 AC3
PCIE_RX0 MGTHRX3_225 AB2 AB1
PCIE_TX1 MGTHTX2_225 AE4 AE3
PCIE_RX1 MGTHRX2_225 AD2 AD1
PCIE_TX2 MGTHTX1_225 AG4 AG3
PCIE_RX2 MGTHRX1_225 AF2 AF1
PCIE_TX3 MGTHTX0_225 AH6 AH5
PCIE_RX3 MGTHRX0_225 AH2 AH1
PCIE_TX4 MGTHTX3_224 AK6 AK5
PCIE_RX4 MGTHRX3_224 AJ4 AJ3
PCIE_TX5 MGTHTX2_224 AL4 AL3
PCIE_RX5 MGTHRX2_224 AK2 AK1
PCIE_TX6 MGTHTX1_224 AM6 AM5
PCIE_RX6 MGTHRX1_224 AM2 AM1
PCIE_TX7 MGTHTX0_224 AN4 AN3
PCIE_RX7 MGTHRX0_224 AP2 AP1
PCIE_TX8 MGTHTX3_227 G4 G3
PCIE_RX8 MGTHRX3_227 F2 F1
PCIE_TX9 MGTHTX2_227 J4 J3
Table 11 : PCI Express Pin Assignments (continued on next page)
Page 10 Functional Description
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