Preface
MicroLogix 1000 Programmable Controllers User Manual
8–10
Double Divide (DDV)
The 32-bit content of the math register is divided by the 16-bit source value and the
rounded quotient is placed in the destination. If the remainder is 0.5 or greater, the
destination is rounded up.
This instruction typically follows a MUL instruction that creates a 32-bit result.
Updates to Arithmetic Status Bits
With this Bit:
The Controller:
S:0/0
Carry (C)
always resets.
S:0/1
Overflow (V)
sets if division by zero or if result is greater than 32,767 or less
than –32,768; otherwise resets. On overflow, the minor error
flag is also set. The value 32,767 is placed in the destination.
S:0/2
Zero (Z)
sets if result is zero; otherwise resets.
S:0/3
Sign (S)
sets if result is negative; otherwise resets; undefined if
overflow is set.
Changes to the Math Register
Initially contains the dividend of the DDV operation. Upon instruction execution
the unrounded quotient is placed in the most significant word of the math register.
The remainder is placed in the least significant word of the math register.
Execution Times
(
µ
sec) when:
True
False
157.06
6.78
DDV
DOUBLE DIVIDE
Source
Dest
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