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KINTEX Ult FPGA Board AXKU040 User Manual

56 / 59

www.alinx.com

Part 17: Power Supply

The power input voltage of the AXKU040 FPGA development board is

DC12V, and the ex12V power supply supplies power to the FPGA
development board.

The Power supply design diagram shown in Figure 18-1.

Figure 17-1: Power Supply Design Diagram

The functions of each power distribution are shown in the following table:

Power Supply

Function

+0.95V

FPGA core voltage

+3.3V

FMC Chip IO Voltage, FMC, SFP, LED, SD Card, Level

Conversion Chip

+1.8V

HDMI Chip, Level Conversion Chip, Power Supply Voltage

+1.2 V/ 1.5A

DDR4, FPGA Chip, Voltage in the FMC

Summary of Contents for AXKU040

Page 1: ...KINTEX UltraScale FPGA Development Board AXKU040 User Manual...

Page 2: ...KINTEX UltraScale FPGA Board AXKU040 User Manual 2 59 www alinx com Version Record Version Date Release By Description Rev 1 1 2021 09 13 Rachel Zhou First Release...

Page 3: ...6 Part 5 2 125Mhz differential clock source 16 Part 5 3 156 25Mhz differential clock source 17 Part 6 USB to Serial Port 19 Part 7 SFP Optical fiber interface 20 Part 8 HDMI Video Output Interface 22...

Page 4: ...nd post application of data processing is possible This product is very suitable for students engineers and other groups engaged in FPGA development AXKU040 FPGA development board mounts four 1GB high...

Page 5: ...on of four optical modules to realize four high speed optical fiber communication interfaces Each fiber optic data communication receives and transmits at speeds of up to 12 5 Gb s USB Uart interface...

Page 6: ...speed input and output signals Temperature and humidity sensor Onboard a temperature and humidity sensor chip LM75 for detecting the temperature and humidity of the environment around the board EEPROM...

Page 7: ...ltraScale FPGA Board AXKU040 User Manual 7 59 www alinx com LED Light 6LEDs 1 power indicator 1 DONE configuration indicator 4 user indicators Key 2 user keys 1 reset key connect to the normal IO of t...

Page 8: ...th 1156 pins and a 1 0mm pitch The chip naming rules for Xilinx KINTEX UltraScale FPGA are shown in Figure 2 1 below Figure 2 1 The Chip Model Definition of KINTEX UltraScale Series The main parameter...

Page 9: ...O are FPGA auxiliary power supply pin connect 1 8V VCCO is the voltage of each BANK of FPGA including BANK0 BANK44 48 BANK64 68 VMGTAVCC is the power supply voltage of the GTH and GTY transceivers ins...

Page 10: ...connected to the BANK44 BANK45 and BANK46 interfaces of the FPGA The specific configuration of DDR4 SDRAM is shown in Table 3 1 Bit Number Chip Model Capacity Factory U45 U47 U48 U49 MT40A512M16LY 06...

Page 11: ...PL_DDR4_DQ13 IO_L11N_T1U_N9_GC_44 AJ24 PL_DDR4_DQ14 IO_L9P_T1L_N4_AD12P_44 AG24 PL_DDR4_DQ15 IO_L12P_T1U_N10_GC_44 AH22 PL_DDR4_DQ16 IO_L14P_T2L_N2_GC_44 AK22 PL_DDR4_DQ17 IO_L17P_T2U_N8_AD10P_44 AL2...

Page 12: ..._46 AK31 PL_DDR4_DQ49 IO_L18P_T2U_N10_AD2P_46 AH34 PL_DDR4_DQ50 IO_L14N_T2L_N3_GC_46 AK32 PL_DDR4_DQ51 IO_L15N_T2L_N5_AD11N_46 AJ31 PL_DDR4_DQ52 IO_L15P_T2L_N4_AD11P_46 AJ30 PL_DDR4_DQ53 IO_L17P_T2U_N...

Page 13: ...AP30 PL_DDR4_DQS6_P IO_L16P_T2U_N6_QBC_AD3P_46 AH33 PL_DDR4_DQS6_N IO_L16N_T2U_N7_QBC_AD3N_46 AJ33 PL_DDR4_DQS7_P IO_L22P_T3U_N6_DBC_AD0P_46 AN34 PL_DDR4_DQS7_N IO_L22N_T3U_N7_DBC_AD0N_46 AP34 PL_DDR4...

Page 14: ...45 AL19 PL_DDR4_CKE IO_L14N_T2L_N3_GC_45 AJ16 PL_DDR4_ACT_B IO_L21N_T3L_N5_AD8N_45 AF18 PL_DDR4_CLK_N IO_L22N_T3U_N7_DBC_AD0N_45 AE15 PL_DDR4_CLK_P IO_L22P_T3U_N6_DBC_AD0P_45 AE16 PL_DDR4_CS_B IO_L21P...

Page 15: ...ASH are shown in Table 4 1 Position Model Capacity Factory U14 N25Q128A 128M Bit Numonyx Table 4 1 QSPI FLASH Specification QSPI FLASH is connected to the dedicated pins of BANK0 of the FPGA chip The...

Page 16: ...ck and other user logic in the FPGA The schematic diagram of the clock source is shown in Figure 5 1 Figure 5 1 200Mhz System Clock Source Schematic System Clock pin assignments Signal Name FPGA Pin S...

Page 17: ...gnal Name FPGA Pin SFP_CLK0_P AF6 SFP_CLK0_N AF5 Part 5 3 156 25Mhz differential clock source A differential 156 25MHz clock source is provided on the FPGA development board to provide the clock to th...

Page 18: ...X UltraScale FPGA Board AXKU040 User Manual 18 59 www alinx com Figure 5 1 156 25Mhz System Clock Source Schematic System Clock pin assignments Signal Name FPGA Pin HDMI_DRU_CLOCK_P H6 HDMI_DRU_CLOCK_...

Page 19: ...cted by a level shifting chip to adapt to different FPGA BANK voltages The USB interface uses the MINI USB interface which can be connected to the USB port of the upper PC for serial data communicatio...

Page 20: ...th 4 RX TX of FPGA BANK24 GTH transceiver Both the TX signal and the RX signal are connected to the FPGA and the optical module through a DC blocking capacitor in a differential signal mode and the da...

Page 21: ...igh level means no light signal is received The 3rd fiber interface FPGA pin assignment is as follows Signal Name FPGA PIN Description SFP3_TX_P AL4 SFP3 Data Transmission Positive SFP3_TX_N AL3 SFP3...

Page 22: ...nterface of ADV7511 are connected to the IO of BANK47 and BANK48 The hardware connection diagram of ADV7511 chip and XCKU040 is shown in Figure 8 1 Figure 8 1 HDMI Output Interface Schematic ADV7511 p...

Page 23: ...HDMI_D11 IO_L20P_T3L_N2_AD1P_48 W30 HDMI Video Signal Data 11 HDMI_D12 IO_L23N_T3U_N9_47 W29 HDMI Video Signal Data 12 HDMI_D13 IO_L23P_T3U_N8_47 V29 HDMI Video Signal Data 13 HDMI_D14 IO_L21P_T3L_N4_...

Page 24: ...lt settings after the GPHY chip is powered on Configuration Pin Instructions Configuration value PHYAD 2 0 MDIO MDC Mode PHY Address PHY Address 011 CLK125_EN Enable 125Mhz clock output selection Enab...

Page 25: ...IO_L4P_T0U_N6_DBC_AD7P_66 B10 Ethernet 1 Transmit Data bit3 PHY1_TXEN IO_L21N_T3L_N5_AD8N_66 B11 Ethernet 1 Transmit Enable Signal PHY1_RXC IO_L14P_T2L_N2_GC_66 H12 Ethernet 1 Receive Clock PHY1_RXD0...

Page 26: ...Ethernet 2 Transmit Data bit3 PHY2_TXEN IO_L10N_T1U_N7_QBC_AD4N _67 A24 Ethernet 2 Transmit Enable Signal PHY2_RXC IO_L13P_T2L_N0_GC_QBC_6 7 D23 Ethernet 2 Receive Clock PHY2_RXD0 IO_L4P_T0U_N6_DBC_AD...

Page 27: ...and cannot be modified The 1 pair speed GTH transceiver signal is connected to BNAK226 The LPC FMC2 expansion port has 33 pairs of differential signals which are respectively connected to the IO of th...

Page 28: ...KINTEX UltraScale FPGA Board AXKU040 User Manual 28 59 www alinx com Figure 10 1 LPC FMC1 Connector Diagram Figure 10 2 LPC FMC2 Connector Diagram...

Page 29: ...U_N8_GC_47 Y23 FMC Reference 1st Reference Clock P FMC1_LPC_CLK0_N IO_L11N_T1U_N9_GC_47 AA23 FMC Reference 1st Reference Clock N FMC1_LPC_CLK1_P IO_L11P_T1U_N8_GC_48 AD30 FMC Reference 2nd Reference C...

Page 30: ...eference 4th Data P FMC1_LPC_LA04_N IO_L7N_T1L_N1_QBC_AD13N_47 AB22 FMC Reference 4th Data N FMC1_LPC_LA05_P IO_L2P_T0L_N2_47 AD25 FMC Reference 5th Data P FMC1_LPC_LA05_N IO_L2N_T0L_N3_47 AD26 FMC Re...

Page 31: ...ata N FMC1_LPC_LA14_P IO_L16P_T2U_N6_QBC_AD3P_47 V22 FMC Reference 14th Data P FMC1_LPC_LA14_N IO_L16N_T2U_N7_QBC_AD3N_47 V23 FMC Reference 14th Data N FMC1_LPC_LA15_P IO_L17P_T2U_N8_AD10P_47 T22 FMC...

Page 32: ...1_LPC_LA23_P IO_L4P_T0U_N6_DBC_AD7P_48 AF29 FMC Reference 23rd Data P FMC1_LPC_LA23_N IO_L4N_T0U_N7_DBC_AD7N_48 AG29 FMC Reference 23rd Data N FMC1_LPC_LA24_P IO_L15P_T2L_N4_AD11P_48 AC34 FMC Referenc...

Page 33: ...N0_DBC_48 AE27 FMC Reference 32nd Data P FMC1_LPC_LA32_N IO_L1N_T0L_N1_DBC_48 AF27 FMC Reference 32nd Data N FMC1_LPC_LA33_P IO_L3P_T0L_N4_AD15P_48 AC28 FMC Reference 33rd Data P FMC1_LPC_LA33_N IO_L3...

Page 34: ...AD6N_64 AL13 FMC Reference 3rd Data N FMC2_LPC_LA04_P IO_L10P_T1U_N6_QBC_AD4P_64 AD11 FMC Reference 4th Data P FMC2_LPC_LA04_N IO_L10N_T1U_N7_QBC_AD4N_64 AE11 FMC Reference 4th Data N FMC2_LPC_LA05_P...

Page 35: ..._T0L_N0_DBC_64 AP11 FMC Reference 13th Data P FMC2_LPC_LA13_N IO_L1N_T0L_N1_DBC_64 AP10 FMC Reference 13th Data N FMC2_LPC_LA14_P IO_L18P_T2U_N10_AD2P_64 AH9 FMC Reference 14th Data P FMC2_LPC_LA14_N...

Page 36: ...R25 FMC Reference 22nd Data P FMC2_LPC_LA22_N IO_L17N_T2U_N9_AD10N_D15_65 R26 FMC Reference 22nd Data N FMC2_LPC_LA23_P IO_L19P_T3L_N0_DBC_AD9P_D10 _65 N22 FMC Reference 23rd Data P FMC2_LPC_LA23_N I...

Page 37: ...BC_RS1_65 G27 FMC Reference 31st Data N FMC2_LPC_LA32_P IO_L6P_T0U_N10_AD6P_A20_65 J23 FMC Reference 32nd Data P FMC2_LPC_LA32_N IO_L6N_T0U_N11_AD6N_A21_65 H24 FMC Reference 32nd Data N FMC2_LPC_LA33_...

Page 38: ...24 FMC LA Reference 0th Data Clock N FMC_HPC_LA01_CC_N IO_L14P_T2L_N2_GC_67 E22 FMC LA Reference 1st Data Clock P FMC_HPC_LA01_CC_P IO_L14N_T2L_N3_GC_67 E23 FMC LA Reference 1st Data Clock N FMC_HPC_L...

Page 39: ...P_67 F23 FMC LA Reference 10th Data P FMC_HPC_LA10_N IO_L21N_T3L_N5_AD8N_67 F24 FMC LA Reference 10th Data N FMC_HPC_LA11_P IO_L18P_T2U_N10_AD2P_67 D20 FMC LA Reference 11th Data P FMC_HPC_LA11_N IO_L...

Page 40: ...ence 19th Data P FMC_HPC_LA19_N IO_L22N_T3U_N7_DBC_AD0N_66 E13 FMC LA Reference 19th Data N FMC_HPC_LA20_P IO_L24P_T3U_N10_66 D13 FMC LA Reference 20th Data P FMC_HPC_LA20_N IO_L24N_T3U_N11_66 C13 FMC...

Page 41: ...erence 28th Data N FMC_HPC_LA29_P IO_L8P_T1L_N2_AD5P_66 J9 FMC LA Reference 29th Data P FMC_HPC_LA29_N IO_L8N_T1L_N3_AD5N_66 H9 FMC LA Reference 29th Data N FMC_HPC_LA30_P IO_L7P_T1L_N0_QBC_AD13P_66 L...

Page 42: ...ce 3rd Data N FMC_HA04_P IO_L16P_T2U_N6_QBC_AD3P_68 G19 FMC HA Reference 4th Data P FMC_HA04_N IO_L16N_T2U_N7_QBC_AD3N_68 F19 FMC HA Reference 4th Data N FMC_HA05_P IO_L10P_T1U_N6_QBC_AD4P_68 D19 FMC...

Page 43: ...B14 FMC HA Reference 13th Data P FMC_HA13_N IO_L1N_T0L_N1_DBC_68 A14 FMC HA Reference 13th Data N FMC_HA14_P IO_L3P_T0L_N4_AD15P_68 B15 FMC HA Reference 14th Data P FMC_HA14_N IO_L3N_T0L_N5_AD15N_68...

Page 44: ...D11P_68 G15 FMC HA Reference 23rd Data P FMC_HA23_N IO_L15N_T2L_N5_AD11N_68 G14 FMC HA Reference 23rd Data N FMC_HPC_SCL IO_T1U_N12_68 C16 FMC I2C Bus Clock FMC_HPC_SDA IO_T2U_N12_68 H14 FMC I2C Bus D...

Page 45: ...Data 7 Input N FMC_DP0_C2M_P MGTHTXP3_228 B6 Transceiver Data 0 Output P FMC_DP0_C2M_N MGTHTXN3_228 B5 Transceiver Data 0 Output N FMC_DP1_C2M_P MGTHTXP2_228 C4 Transceiver Data 1 Output P FMC_DP1_C2M...

Page 46: ...KINTEX UltraScale FPGA Board AXKU040 User Manual 46 59 www alinx com N FMC_DP7_C2M_P MGTHTXP0_227 N4 Transceiver Data 7 Output P FMC_DP7_C2M_N MGTHTXN0_227 N3 Transceiver Data 7 Output N...

Page 47: ...f vendors These include IBM Microsoft Motorola NEC Samsung and others Driven by these leading manufacturers SD cards have become the most widely used memory card in consumer digital devices The AXKU04...

Page 48: ...r Description SD_CLK IO_L22P_T3U_N6_DBC_AD0P_64 AN8 SD Clock Signal SD_CMD IO_L21N_T3L_N5_AD8N_64 AL9 SD Command Signal SD_D0 IO_L24N_T3U_N11_64 AL8 SDData0 SD_D1 IO_L22N_T3U_N7_DBC_AD0N_64 AP8 SDData...

Page 49: ...addition two SATA ports are reserved on the FPGA board for connecting solid state drives The schematic diagram of FPGA and SMA interface connection is shown in Figure 12 1 Figure 12 1 SMA Connection S...

Page 50: ...t Signal Name FPGA Pin FPGA Pin Number Description SATA1_ TX_P MGTHTXP0_225 AH6 SATA1 Data Transmission P SATA1_ TX_N MGTHTXN0_225 AH5 SATA1 Data Transmission N SATA1_ RX_P MGTHRXP0_225 AH2 SATA1 Data...

Page 51: ...LM75 of ON Semiconductor The temperature accuracy of the LM75 chip is 0 5 degrees The sensor and FPGA are directly connected to the I2C digital interface The FPGA reads the temperature near the curren...

Page 52: ...to the FPGA chip caused by hot plugging a protection diode is added to the JTAG signal to ensure that the voltage of the signal is within the range accepted by the FPGA to avoid damage of the FPGA chi...

Page 53: ...ght up 4 user LEDs are connected to the IO of the FPGA BANK65 the user can control the lighting and extinction through the program When the IO voltage connected to the user LED is configured low level...

Page 54: ...lights Signal Name FPGA Pin FPGA Pin Number Description LED1 IO_L22N_T3U_N7_DBC_AD0N_D05_65 L20 User LED1 LED2 IO_L22P_T3U_N6_DBC_AD0P_D04_65 M20 User LED2 LED3 IO_L23N_T3U_N9_I2C_SDA_65 M21 User LED3...

Page 55: ...ctive at low level to realize some functions of the board for customers The reset key is connected to FPGA BANK64 for system reset The circuit of user key part is shown in Figure 16 1 Figure 16 1 Keys...

Page 56: ...o the FPGA development board The Power supply design diagram shown in Figure 18 1 Figure 17 1 Power Supply Design Diagram The functions of each power distribution are shown in the following table Powe...

Page 57: ...alinx com 1 2 V 500mA Auxiliary Voltage Gigabit Chip MGTAVCC 1 0V FPGA Chip Voltage MGTAVTT 1 2V FPGA Chip Voltage DDRVTT 0 6V DDR4 pull up voltage FMC2_VADJ 1 8V FPGA chip voltage Level shift voltag...

Page 58: ...he chip from overheating The control of the fan is controlled by the FPGA Chip The control pin is connected to the IO of the BANK65 If the IO level output is high the MOSFET is turned on and the fan i...

Page 59: ...KINTEX UltraScale FPGA Board AXKU040 User Manual 59 59 www alinx com Part 19 Form Factory Figure 19 1 Form Factor Top View...

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