manualshive.com logo in svg

Alinx AV7K325, User Manual, Page: 39 / 54

Share
Download
Alinx AV7K325 User Manual Download Page 39

KINTEX-7 FPGA Development Board AV7K325 User Manual

39 / 54

Amazon Store: https://www.amazon.com/alinx

9136_TX1_SCK

B13_L7_P

AC29

I2S serial clock

9136_TX1_WS

B13_L12_N

AC27

I2S byte select signal

9136_TX1_I2S0

B13_L12_P

AB27

I2S data 0

9136_TX1_I2S1

B13_L1_P

Y26

I2S data 1

9136_TX1_I2S2

B13_L1_N

AA26

I2S data 2

9136_TX1_I2S3

B13_L4_N

Y29

I2S data 3

9136_TX1_SPDIF

B13_L4_P

W29

S/PDIF signal

9136_NRESET

B12_L12_P

AD23

Chip reset signal

HDMI1_SCL

B13_L8_P

Y30

HDMI IIC control clock

HDMI1_SDA

B13_L8_N

AA30

HDMI IIC control data

The pin assignment of the 2

nd

HDMI output:

Signal Name

FPGA Pin

Pin

Number

Description

9136_TX2_D0

B18_L11_N

G14

Video output signal data 0

9136_TX2_D1

B18_L11_P

H14

Video output signal data 1

9136_TX2_D2

B18_L20_N

E15

Video output signal data 2

9136_TX2_D3

B18_L20_P

E14

Video output signal data 3

9136_TX2_D4

B18_L10_N

H12

Video output signal data 4

9136_TX2_D5

B18_L10_P

H11

Video output signal data 5

9136_TX2_D6

B18_L12_N

F13

Video output signal data 6

9136_TX2_D7

B18_L12_P

G13

Video output signal data 7

9136_TX2_D8

B18_L4_N

J13

Video output signal data 8

9136_TX2_D9

B18_L4_P

K13

Video output signal data 9

9136_TX2_D10

B18_L1_N

K16

Video output signal data 10

9136_TX2_D11

B18_L1_P

L16

Video output signal data 11

9136_TX2_D12

B18_L2_N

K15

Video output signal data 12

9136_TX2_D13

B18_L2_P

L15

Video output signal data 13

9136_TX2_D14

B18_L3_N

L13

Video output signal data 14

9136_TX2_D15

B18_L3_P

L12

Video output signal data 15

9136_TX2_D16

B18_L5_P

K14

Video output signal data 16

9136_TX2_D17

B18_L5_N

J14

Video output signal data 17

Summary of Contents for AV7K325

Page 1: ...KINTEX 7 FPGA Development Board AV7K325 User Manual...

Page 2: ...KINTEX 7 FPGA Development Board AV7K325 User Manual 2 54 Amazon Store https www amazon com alinx Version Record Version Date Release By Description Rev 1 0 2020 12 01 Rachel Zhou First Release...

Page 3: ...z system clock source 17 Part 2 5 2 GTX Reference Clock 18 Part 2 6 LED Light 19 Part 2 7 Power Supply 20 Part 2 8 Size Dimension 23 Part 2 9 Board to Board Pin Definition 23 Part 3 Carrier Board 32 P...

Page 4: ...KINTEX 7 FPGA Development Board AV7K325 User Manual 4 54 Amazon Store https www amazon com alinx Part 3 13 Size Dimension 54...

Page 5: ...d we have extended a wealth of interfaces for users such as 1 PCIex8 interface 4 SFP interface 2 HDMI output interface 2 HDMI input interface 2 SATA interface 1 UART serial port 1 SD card slot 1 40 pi...

Page 6: ...Xilinx s KINTEX 7 series chip model XC7K325TFFG900 Four DDR3 memory chips are connected to the HP port of the FPGA chip Each DDR3 has a capacity of up to 512M bytes forming a 64 bit data bandwidth A 1...

Page 7: ...terface and the single channel communication rate can be as high as 5GBaud 4 SFP interfaces The four high speed transceivers of the GTX transceiver of the FPGA are connected to the transmission and re...

Page 8: ...ch expansion port can be connected to various ALINX modules binocular camera TFT LCD screen high speed AD module etc Expansion ports include 1 5V power supply 2 3 3V power supplies 3 ground and 34 IO...

Page 9: ...nd system files The 4 board to board connectors of this core board extend 276 IOs of which the level of 92 IOs of BANK17 and BANK18 can be modified by replacing the LDO chip on the core board to meet...

Page 10: ...d the temperature class is industrial This model is a FGG900 package with 900 pins and a 1 0mm pitch The chip naming rules for Xilinx KINTEX 7 FPGA are shown in Figure 2 2 1 below Figure 2 2 1 The Spe...

Page 11: ...at speeds up to 800MHz data rate 1600Mbps and four DDR3 memory systems are directly connected to the BANK32 BANK33 and BANK34 interfaces of the FPGA The specific configuration of DDR3 SDRAM is shown...

Page 12: ...R3_D0 IO_L13P_T2_MRCC_32 AD18 DDR3_D1 IO_L16N_T2_32 AB18 DDR3_D2 IO_L14P_T2_SRCC_32 AD17 DDR3_D3 IO_L17P_T2_32 AB19 DDR3_D4 IO_L14N_T2_SRCC_32 AD16 DDR3_D5 IO_L17N_T2_32 AC19 DDR3_D6 IO_L13N_T2_MRCC_3...

Page 13: ...32 AC14 DDR3_D27 IO_L20P_T3_32 AA15 DDR3_D28 IO_L23P_T3_32 AA17 DDR3_D29 IO_L22N_T3_32 AD14 DDR3_D30 IO_L23N_T3_32 AA16 DDR3_D31 IO_L20N_T3_32 AB15 DDR3_D32 IO_L22N_T3_34 AK6 DDR3_D33 IO_L23P_T3_34 AJ...

Page 14: ...0 IO_L16P_T2_32 AA18 DDR3_DM1 IO_L12P_T1_MRCC_32 AF17 DDR3_DM2 IO_L6P_T0_32 AE16 DDR3_DM3 IO_L24N_T3_32 Y15 DDR3_DM4 IO_L20P_T3_34 AF7 DDR3_DM5 IO_L7P_T1_34 AF3 DDR3_DM6 IO_L18P_T2_34 AJ3 DDR3_DM7 IO_...

Page 15: ...D8 DDR3_A12 IO_L7P_T1_33 AB10 DDR3_A13 IO_L7N_T1_33 AC10 DDR3_A14 IO_L15P_T2_DQS_33 AJ9 DDR3_BA0 IO_L8N_T1_33 AE8 DDR3_BA1 IO_L9P_T1_DQS_33 AC12 DDR3_BA2 IO_L9N_T1_DQS_33 AC11 DDR3_WE IO_L10P_T1_33 AD...

Page 16: ...ected to the dedicated pins of BANK0 and BANK14 of the FPGA chip The clock pin is connected to CCLK0 of BANK0 and other data and chip select signals are connected to D00 D03 and FCS pins of BANK14 res...

Page 17: ...schematic diagram of the clock circuit design is shown in Figure 2 5 1 Figure 2 5 1 Clock Source in the Core Board Part 2 5 1 200Mhz system clock source The FPGA core board provides a differential 20...

Page 18: ...ic System Clock pin assignments Signal Name FPGA Pin SYS_CLK_P AE10 SYS_CLK_N AF10 Part 2 5 2 GTX Reference Clock The AC7K325 core board provides a 125Mhz reference clock for the GTX transceiver The r...

Page 19: ...BANK117_CLK1_P J8 BANK117_CLK1_N J7 Part 2 6 LED Light There are 2 red LED lights on the AC7K325 core board one of which is the power indicator PWR and the other is the configuration LED DONE The pow...

Page 20: ...4 Amazon Store https www amazon com alinx Figure 2 6 1 LED in core board Schematic Part 2 7 Power Supply The AC7K325 core board power supply voltage is DC5V which is powered by the carrier board The c...

Page 21: ...2 7 1 Power Supply Design Diagram 5V generates 1 0V FPGA core power through the DCDC power chip EM2130L01QI The output current of EM2130 is up to 20A which meets the current demand of the core voltag...

Page 22: ...LDO chip SPX3819 1 8 The VTT and VREF voltages of DDR3 are generated by TPS51200 In addition the IO power supply of BANK17 and BANK18 is generated through 2 SPX3819M5 3 3 Users can change the LDO chi...

Page 23: ...total of 4 high speed expansion ports using 4 120 Pin inter board connectors J29 J32 to connect to the carrier board The connector uses Panasonic s AXK5A2137YG and the corresponding connector model is...

Page 24: ...GND 19 BANK115_TX3_N T1 20 BANK115_RX3_N V5 21 BANK115_TX3_P T2 22 BANK115_RX3_P V6 23 GND 24 GND 25 BANK115_CLK0_N R7 26 BANK115_CLK1_N U7 27 BANK115_CLK0_P R8 28 BANK115_CLK1_N U8 29 GND 30 GND 31 B...

Page 25: ...18_RX1_N D5 81 BANK117_RX1_P H6 82 BANK118_RX1_P D6 83 GND 84 GND 85 BANK117_TX2_N H1 86 BANK118_TX2_N B1 87 BANK117_TX2_P H2 88 BANK118_TX2_P B2 89 GND 90 GND 91 BANK117_RX2_N G3 92 BANK118_RX2_N B5...

Page 26: ...L8_N J12 18 B18_L4_N J13 19 GND 20 GND 21 B18_L9_P J16 22 B18_L12_P G13 23 B18_L9_N H16 24 B18_L12_N F13 25 B18_L16_P F11 26 B18_L10_P H11 27 B18_L16_N E11 28 B18_L10_N H12 29 GND 30 GND 31 B18_L18_P...

Page 27: ...D 81 B17_L24_P C19 82 B17_L23_N A22 83 B17_L24_N B19 84 B17_L23_P B22 85 B17_L18_N F17 86 B17_L12_P F20 87 B17_L18_P G17 88 B17_L12_N E20 89 GND 90 GND 91 B17_L19_N B20 92 B17_L11_N E21 93 B17_L19_P C...

Page 28: ...0 17 B16_L13_P D27 18 B16_L18_P E29 19 GND 20 GND 21 B16_L21_P G27 22 B16_L14_N D28 23 B16_L21_N F27 24 B16_L14_P E28 25 B16_L20_N F28 26 B16_L22_N F30 27 B16_L20_P G28 28 B16_L22_P G29 29 GND 30 GND...

Page 29: ...B15_L2_N L23 82 B15_L21_N N24 83 B15_L2_P L22 84 B15_L21_P P23 85 B15_L13_P K28 86 B15_L12_N K25 87 B15_L13_N K29 88 B15_L12_P L25 89 GND 90 GND 91 B15_L22_N P22 92 B15_L20_N N22 93 B15_L22_P P21 94 B...

Page 30: ...18 B13_L5_P AA27 19 GND U14 20 GND U14 21 B13_L18_P AG30 22 B13_L2_N W28 23 B13_L18_N AH30 24 B13_L2_P W27 25 B13_L21_N AG28 26 B13_L8_P Y30 27 B13_L21_P AG27 28 B13_L8_N AA30 29 GND U14 30 GND U14 3...

Page 31: ...H25 78 B12_L4_P AA22 79 GND U14 80 GND U14 81 B12_L15_N AK25 82 B12_L1_P Y23 83 B12_L15_P AJ24 84 B12_L1_N Y24 85 B12_L17_N AK24 86 B12_L2_P Y21 87 B12_L17_P AK23 88 B12_L2_N AA21 89 GND U14 90 GND U1...

Page 32: ...independent buttons 2 user LED lights Part 3 2 SFP Interface The AV7K325 FPGA development board has four optical interfaces Users can purchase SFP optical modules 1 25G 2 5Goptical modules on the mar...

Page 33: ...a Receiver Negative SFP2_TX_P BANK117_TX1_P J4 SFP 2 Data Transmitter Positive SFP2_TX_N BANK117_TX1_N J3 SFP 2 Data Transmitter Negative SFP2_RX_P BANK117_RX1_P H6 SFP 2 Data Receiver Positive SFP2_R...

Page 34: ...e card electrical specifications and can be used directly on the x8 PCIe slot of a normal PC Data communication between PCIEex8 PCIEex4 PCIex2 and PCIex1 can be realized between the FPGA development b...

Page 35: ...Receive Negative PCIE_RX1_P BANK116_RX2_P P6 PCIE Channel 1 Data Receive Positive PCIE_RX1_N BANK116_RX2_N P5 PCIE Channel 1 Data Receive Negative PCIE_RX2_P BANK116_RX1_P R4 PCIE Channel 2 Data Recei...

Page 36: ...Receive Positive PCIE_TX3_N BANK116_TX0_N P1 PCIE Channel 3 Data Receive Negative PCIE_TX4_P BANK115_TX3_P T2 PCIE Channel 4 Data Receive Positive PCIE_TX4_N BANK115_TX3_N T1 PCIE Channel 4 Data Recei...

Page 37: ...e 1st HDMI output Signal Name FPGA Pin Pin Number Description 9136_TX1_D0 B17_L12_N E20 Video output signal data 0 9136_TX1_D1 B17_L12_P F20 Video output signal data 1 9136_TX1_D2 B17_L23_P B22 Video...

Page 38: ..._P D21 Video output signal data 22 9136_TX1_D23 B17_L8_N C21 Video output signal data 23 9136_TX1_D24 B17_L24_P C19 Video output signal data 24 9136_TX1_D25 B17_L24_N B19 Video output signal data 25 9...

Page 39: ...H14 Video output signal data 1 9136_TX2_D2 B18_L20_N E15 Video output signal data 2 9136_TX2_D3 B18_L20_P E14 Video output signal data 3 9136_TX2_D4 B18_L10_N H12 Video output signal data 4 9136_TX2_...

Page 40: ...Video output signal data 30 9136_TX2_D31 B18_L15_N B12 Video output signal data 31 9136_TX2_D32 B18_L23_P C15 Video output signal data 32 9136_TX2_D33 B18_L23_N B15 Video output signal data 33 9136_TX...

Page 41: ...30Hz input and data output in different formats In addition the EDID data of HDMI is configured by the FPGA internal program the I2C bus is connected to the HDMI interface through the level conversio...

Page 42: ...L25 Video input signal data 13 HDMI1_IN_D14 B15_L12_N K25 Video input signal data 14 HDMI1_IN_D15 B15_L21_P P23 Video input signal data 15 HDMI1_IN_D16 B15_L21_N N24 Video input signal data 16 HDMI1_I...

Page 43: ...N J24 Video input signal data 43 HDMI1_IN_D44 B15_L10_P K26 Video input signal data 44 HDMI1_IN_D45 B15_L10_N J26 Video input signal data 45 HDMI1_IN_D46 B15_L14_P M28 Video input signal data 46 HDMI1...

Page 44: ...HDMI2_IN_D7 B16_L13_N C27 Video input signal data 7 HDMI2_IN_D8 B16_L13_P D27 Video input signal data 8 HDMI2_IN_D9 B16_L21_P G27 Video input signal data 9 HDMI2_IN_D10 B16_L21_N F27 Video input sign...

Page 45: ...16_L23_N H27 Video input signal data 36 HDMI2_IN_D37 B16_L23_P H26 Video input signal data 37 HDMI2_IN_D38 B16_L17_P B30 Video input signal data 38 HDMI2_IN_D39 B16_L17_N A30 Video input signal data 3...

Page 46: ...ata signal HDMI2_IN_AP5 B13_L17_N AJ29 Audio data signal HDMI2_IN_DSCL B18_L24_P B14 EDID I2C clock HDMI2_IN_DSDA B18_L24_N A15 EDID I2C data HDMI2_SCL B13_L11_N AD28 HDMI I2C clock HDMI2_SDA B13_L11_...

Page 47: ...ATA1 Channel Data Transmitting Negative SATA2_TX_P BANK118_TX0_P D2 SATA1 Channel Data Transmitting Positive SATA2_RX_N BANK118_RX0_N E3 SATA1 Channel Data Receiving Negative SATA2_RX_P BANK118_RX0_P...

Page 48: ..._L5_P AAJ27 Uart Data Input UART_TX B13_L2_N W28 Uart Data Output Part 3 8 SD Card Slot The AV7K7325 development board includes a Micro SD card interface to provide users with access to SD card memory...

Page 49: ...D29 SD Data1 SD_D2 B13_L9_N AE29 SD Data2 SD_D3 B13_L6_N AB25 SD Data3 Part 3 9 40 Pin Expansion Port The AV7K325 FPGA development board is reserved with one 0 1 inch spacing standard 40 pin expansion...

Page 50: ...AK25 15 IO1_7N AH25 16 IO1_7P AG25 17 IO1_8N AG23 18 IO1_8P AF22 19 IO1_9N AC21 20 IO1_9P AC20 21 IO1_10N AB23 22 IO1_10P AB22 23 IO1_11N AD21 24 IO1_11P AE21 25 IO1_12N AB20 26 IO1_12P AA20 27 IO1_1...

Page 51: ...is on When the connected IO voltage is high the user LED will be extinguished In addition there are 2 user buttons on the board The default button signal is high When the button is pressed the button...

Page 52: ...mage to the FPGA chip caused by hot plugging a protection diode is added to the JTAG signal to ensure that the voltage of the signal is within the range accepted by the FPGA to avoid damage of the FPG...

Page 53: ...nter board connector the current output of the DCDC power supply is 6A and the current output of the other three power supplies is 2A The schematic of the power supply design on the board is shown in...

Page 54: ...KINTEX 7 FPGA Development Board AV7K325 User Manual 54 54 Amazon Store https www amazon com alinx Part 3 13 Size Dimension Figure 3 13 1 Carrier Board Size Dimension...

Reviews:

No comments