KINTEX-7 FPGA Development Board AV7K325 User Manual
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Figure 2-5-2: 200Mhz System Clock Source Schematic
System Clock pin assignments:
Signal Name
FPGA Pin
SYS_CLK_P
AE10
SYS_CLK_N
AF10
Part 2.5.2: GTX Reference Clock
The AC7K325 core board provides a 125Mhz reference clock for the GTX
transceiver. The reference clock is connected to the reference clock input
REFCLK1P/REFCLK1N of BANK117. The schematic of this clock source is
shown in Figure 2-5-3